acquistion.syr

CPLD初始化程序-用于DSP5416与SAA7111A的时序控制初始化

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: acquistion.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : acquistion.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : acquistion
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Top Module Name                    : acquistion
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : acquistion.lso
verilog2001                        : YES
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx/bin/aquisition_test/test.vhdl in Library work.
Architecture structure of Entity acquistion is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <acquistion> (Architecture <structure>).
WARNING:Xst:819 - C:/Xilinx/bin/aquisition_test/test.vhdl line 64: The following signals are missing in the process sensitivity list:
   tempdivclk1.
WARNING:Xst:819 - C:/Xilinx/bin/aquisition_test/test.vhdl line 75: The following signals are missing in the process sensitivity list:
   count.
WARNING:Xst:819 - C:/Xilinx/bin/aquisition_test/test.vhdl line 87: The following signals are missing in the process sensitivity list:
   tempdivclk2.
Entity <acquistion> analyzed. Unit <acquistion> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <acquistion>.
    Related source file is C:/Xilinx/bin/aquisition_test/test.vhdl.
    Found 2-bit up counter for signal <count>.
    Found 1-bit register for signal <q1>.
    Found 1-bit register for signal <q2>.
    Found 1-bit register for signal <tempdivclk1>.
    Found 1-bit register for signal <tempdivclk2>.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
Unit <acquistion> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 2-bit up counter                  : 1
# Registers                        : 4
 1-bit register                    : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <acquistion> ...
  implementation constraint: INIT=r	 : tempdivclk1
  implementation constraint: INIT=r	 : tempdivclk2

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : acquistion.ngr
Top Level Output File Name         : acquistion
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : xc9500xl
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 10

Macro Statistics :
# Registers                        : 4
#      1-bit register              : 4
# Xors                             : 1
#      1-bit xor2                  : 1

Cell Usage :
# BELS                             : 19
#      AND2                        : 8
#      INV                         : 10
#      XOR2                        : 1
# FlipFlops/Latches                : 6
#      FD                          : 4
#      FDC                         : 2
# IO Buffers                       : 10
#      IBUF                        : 6
#      OBUF                        : 4
=========================================================================
CPU : 1.77 / 2.86 s | Elapsed : 2.00 / 3.00 s
 
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