_info

CPLD初始化程序-用于DSP5416与SAA7111A的时序控制初始化

m255
cModel Technology
dC:\Xilinx\bin\aquisition_test
Eacquistion
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1174896414
Ftest.vhdl
l0
L5
V8X<?jW:_SdeKekdBo_ijd1
OE;C;5.7d;15
31
o-93 -explicit
tExplicit T
Astructure
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work acquistion 8X<?jW:_SdeKekdBo_ijd1
l19
L12
VRb4NO^?Q1JEdLZl;F]>lG1
OE;C;5.7d;15
31
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
o-93 -explicit
tExplicit T