69_tb_decoder.vhd

vhdl very good debug release vhdl very good debug release

library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;

entity tb_decoder is
end tb_decoder;

architecture tb of tb_decoder is
component decoder
          port(keypad:in std_logic_vector(9 downto 0);
               value :out t_digital);
end component;

signal keypad:std_logic_vector(9 downto 0);
signal value :t_digital;

for all:decoder use entity work.decoder(rtl);

begin
u1:decoder port map(keypad,value);

  process
  begin
  keypad <= "0000000001" ,
            "0000000010" after 100 ns,
            "0000000100" after 200 ns,
            "0000001000" after 300 ns,
            "0000010000" after 400 ns,
            "0000100000" after 500 ns,
            "0001000000" after 600 ns,
            "0001000000" after 700 ns,            
            "0010000000" after 800 ns,
            "0100000000" after 900 ns,
            "1000000000" after 1000 ns,
            "0000010001" after 1100 ns;
  wait for 1200 ns;
  assert false report "End of simulation!"
  severity error;
  end process;
end tb;