timer.tan.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "ITDB_TH_RESULT" "dff_A Sw_n\[0\] Clk -4.494 ns register " "Info: th for register \"dff_A\" (data pin = \"Sw_n\[0\]\", clock pin = \"Clk\") is -4.494 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.860 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to destination register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'Clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.915 ns) + CELL(0.666 ns) 2.860 ns dff_A 3 REG LCFF_X32_Y13_N27 1 " "Info: 3: + IC(0.915 ns) + CELL(0.666 ns) = 2.860 ns; Loc. = LCFF_X32_Y13_N27; Fanout = 1; REG Node = 'dff_A'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { Clk~clkctrl dff_A } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.15 % ) " "Info: Total cell delay = 1.806 ns ( 63.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.054 ns ( 36.85 % ) " "Info: Total interconnect delay = 1.054 ns ( 36.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { Clk Clk~clkctrl dff_A } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { Clk {} Clk~combout {} Clk~clkctrl {} dff_A {} } { 0.000ns 0.000ns 0.139ns 0.915ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.660 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns Sw_n\[0\] 1 PIN PIN_161 1 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_161; Fanout = 1; PIN Node = 'Sw_n\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sw_n[0] } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.206 ns) + CELL(0.460 ns) 7.660 ns dff_A 2 REG LCFF_X32_Y13_N27 1 " "Info: 2: + IC(6.206 ns) + CELL(0.460 ns) = 7.660 ns; Loc. = LCFF_X32_Y13_N27; Fanout = 1; REG Node = 'dff_A'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.666 ns" { Sw_n[0] dff_A } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 18.98 % ) " "Info: Total cell delay = 1.454 ns ( 18.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.206 ns ( 81.02 % ) " "Info: Total interconnect delay = 6.206 ns ( 81.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.660 ns" { Sw_n[0] dff_A } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.660 ns" { Sw_n[0] {} Sw_n[0]~combout {} dff_A {} } { 0.000ns 0.000ns 6.206ns } { 0.000ns 0.994ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { Clk Clk~clkctrl dff_A } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { Clk {} Clk~combout {} Clk~clkctrl {} dff_A {} } { 0.000ns 0.000ns 0.139ns 0.915ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.660 ns" { Sw_n[0] dff_A } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.660 ns" { Sw_n[0] {} Sw_n[0]~combout {} dff_A {} } { 0.000ns 0.000ns 6.206ns } { 0.000ns 0.994ns 0.460ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Peak virtual memory: 125 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 22:13:50 2008 " "Info: Processing ended: Wed Jul 02 22:13:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}