timer.tan.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Cout\[22\] " "Info: Detected ripple clock \"Cout\[22\]\" as buffer" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 45 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Cout\[22\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register Timer_Cout:Timer_Cout_A\|min_L\[2\] register Timer_Disp:Timer_Disp_A\|decorder_sel\[2\] 145.73 MHz 6.862 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 145.73 MHz between source register \"Timer_Cout:Timer_Cout_A\|min_L\[2\]\" and destination register \"Timer_Disp:Timer_Disp_A\|decorder_sel\[2\]\" (period= 6.862 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.641 ns + Longest register register " "Info: + Longest register to register delay is 1.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Timer_Cout:Timer_Cout_A\|min_L\[2\] 1 REG LCFF_X29_Y14_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y14_N3; Fanout = 5; REG Node = 'Timer_Cout:Timer_Cout_A\|min_L\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Timer_Cout:Timer_Cout_A|min_L[2] } "NODE_NAME" } } { "Timer_Cout.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Cout.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.747 ns) + CELL(0.206 ns) 0.953 ns Timer_Disp:Timer_Disp_A\|Mux1~82 2 COMB LCCOMB_X30_Y14_N2 1 " "Info: 2: + IC(0.747 ns) + CELL(0.206 ns) = 0.953 ns; Loc. = LCCOMB_X30_Y14_N2; Fanout = 1; COMB Node = 'Timer_Disp:Timer_Disp_A\|Mux1~82'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.953 ns" { Timer_Cout:Timer_Cout_A|min_L[2] Timer_Disp:Timer_Disp_A|Mux1~82 } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.206 ns) 1.533 ns Timer_Disp:Timer_Disp_A\|Mux1~83 3 COMB LCCOMB_X30_Y14_N20 1 " "Info: 3: + IC(0.374 ns) + CELL(0.206 ns) = 1.533 ns; Loc. = LCCOMB_X30_Y14_N20; Fanout = 1; COMB Node = 'Timer_Disp:Timer_Disp_A\|Mux1~83'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.580 ns" { Timer_Disp:Timer_Disp_A|Mux1~82 Timer_Disp:Timer_Disp_A|Mux1~83 } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.641 ns Timer_Disp:Timer_Disp_A\|decorder_sel\[2\] 4 REG LCFF_X30_Y14_N21 7 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.641 ns; Loc. = LCFF_X30_Y14_N21; Fanout = 7; REG Node = 'Timer_Disp:Timer_Disp_A\|decorder_sel\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Timer_Disp:Timer_Disp_A|Mux1~83 Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.520 ns ( 31.69 % ) " "Info: Total cell delay = 0.520 ns ( 31.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.121 ns ( 68.31 % ) " "Info: Total interconnect delay = 1.121 ns ( 68.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.641 ns" { Timer_Cout:Timer_Cout_A|min_L[2] Timer_Disp:Timer_Disp_A|Mux1~82 Timer_Disp:Timer_Disp_A|Mux1~83 Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.641 ns" { Timer_Cout:Timer_Cout_A|min_L[2] {} Timer_Disp:Timer_Disp_A|Mux1~82 {} Timer_Disp:Timer_Disp_A|Mux1~83 {} Timer_Disp:Timer_Disp_A|decorder_sel[2] {} } { 0.000ns 0.747ns 0.374ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.957 ns - Smallest " "Info: - Smallest clock skew is -4.957 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.864 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'Clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.666 ns) 2.864 ns Timer_Disp:Timer_Disp_A\|decorder_sel\[2\] 3 REG LCFF_X30_Y14_N21 7 " "Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X30_Y14_N21; Fanout = 7; REG Node = 'Timer_Disp:Timer_Disp_A\|decorder_sel\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { Clk~clkctrl Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.06 % ) " "Info: Total cell delay = 1.806 ns ( 63.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.058 ns ( 36.94 % ) " "Info: Total interconnect delay = 1.058 ns ( 36.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { Clk Clk~clkctrl Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Timer_Disp:Timer_Disp_A|decorder_sel[2] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 7.821 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 7.821 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.285 ns) + CELL(0.970 ns) 4.395 ns Cout\[22\] 2 REG LCFF_X2_Y16_N21 3 " "Info: 2: + IC(2.285 ns) + CELL(0.970 ns) = 4.395 ns; Loc. = LCFF_X2_Y16_N21; Fanout = 3; REG Node = 'Cout\[22\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.255 ns" { Clk Cout[22] } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.841 ns) + CELL(0.000 ns) 6.236 ns Cout\[22\]~clkctrl 3 COMB CLKCTRL_G3 13 " "Info: 3: + IC(1.841 ns) + CELL(0.000 ns) = 6.236 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'Cout\[22\]~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.841 ns" { Cout[22] Cout[22]~clkctrl } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.666 ns) 7.821 ns Timer_Cout:Timer_Cout_A\|min_L\[2\] 4 REG LCFF_X29_Y14_N3 5 " "Info: 4: + IC(0.919 ns) + CELL(0.666 ns) = 7.821 ns; Loc. = LCFF_X29_Y14_N3; Fanout = 5; REG Node = 'Timer_Cout:Timer_Cout_A\|min_L\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { Cout[22]~clkctrl Timer_Cout:Timer_Cout_A|min_L[2] } "NODE_NAME" } } { "Timer_Cout.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Cout.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 35.49 % ) " "Info: Total cell delay = 2.776 ns ( 35.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.045 ns ( 64.51 % ) " "Info: Total interconnect delay = 5.045 ns ( 64.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.821 ns" { Clk Cout[22] Cout[22]~clkctrl Timer_Cout:Timer_Cout_A|min_L[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.821 ns" { Clk {} Clk~combout {} Cout[22] {} Cout[22]~clkctrl {} Timer_Cout:Timer_Cout_A|min_L[2] {} } { 0.000ns 0.000ns 2.285ns 1.841ns 0.919ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { Clk Clk~clkctrl Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Timer_Disp:Timer_Disp_A|decorder_sel[2] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.821 ns" { Clk Cout[22] Cout[22]~clkctrl Timer_Cout:Timer_Cout_A|min_L[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.821 ns" { Clk {} Clk~combout {} Cout[22] {} Cout[22]~clkctrl {} Timer_Cout:Timer_Cout_A|min_L[2] {} } { 0.000ns 0.000ns 2.285ns 1.841ns 0.919ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "Timer_Cout.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Cout.v" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 37 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.641 ns" { Timer_Cout:Timer_Cout_A|min_L[2] Timer_Disp:Timer_Disp_A|Mux1~82 Timer_Disp:Timer_Disp_A|Mux1~83 Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.641 ns" { Timer_Cout:Timer_Cout_A|min_L[2] {} Timer_Disp:Timer_Disp_A|Mux1~82 {} Timer_Disp:Timer_Disp_A|Mux1~83 {} Timer_Disp:Timer_Disp_A|decorder_sel[2] {} } { 0.000ns 0.747ns 0.374ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { Clk Clk~clkctrl Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Timer_Disp:Timer_Disp_A|decorder_sel[2] {} } { 0.000ns 0.000ns 0.139ns 0.919ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.821 ns" { Clk Cout[22] Cout[22]~clkctrl Timer_Cout:Timer_Cout_A|min_L[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.821 ns" { Clk {} Clk~combout {} Cout[22] {} Cout[22]~clkctrl {} Timer_Cout:Timer_Cout_A|min_L[2] {} } { 0.000ns 0.000ns 2.285ns 1.841ns 0.919ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dff_A Sw_n\[0\] Clk 4.760 ns register " "Info: tsu for register \"dff_A\" (data pin = \"Sw_n\[0\]\", clock pin = \"Clk\") is 4.760 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.660 ns + Longest pin register " "Info: + Longest pin to register delay is 7.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns Sw_n\[0\] 1 PIN PIN_161 1 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_161; Fanout = 1; PIN Node = 'Sw_n\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sw_n[0] } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.206 ns) + CELL(0.460 ns) 7.660 ns dff_A 2 REG LCFF_X32_Y13_N27 1 " "Info: 2: + IC(6.206 ns) + CELL(0.460 ns) = 7.660 ns; Loc. = LCFF_X32_Y13_N27; Fanout = 1; REG Node = 'dff_A'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.666 ns" { Sw_n[0] dff_A } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 18.98 % ) " "Info: Total cell delay = 1.454 ns ( 18.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.206 ns ( 81.02 % ) " "Info: Total interconnect delay = 6.206 ns ( 81.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.660 ns" { Sw_n[0] dff_A } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.660 ns" { Sw_n[0] {} Sw_n[0]~combout {} dff_A {} } { 0.000ns 0.000ns 6.206ns } { 0.000ns 0.994ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.860 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk\" to destination register is 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'Clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.915 ns) + CELL(0.666 ns) 2.860 ns dff_A 3 REG LCFF_X32_Y13_N27 1 " "Info: 3: + IC(0.915 ns) + CELL(0.666 ns) = 2.860 ns; Loc. = LCFF_X32_Y13_N27; Fanout = 1; REG Node = 'dff_A'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { Clk~clkctrl dff_A } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.15 % ) " "Info: Total cell delay = 1.806 ns ( 63.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.054 ns ( 36.85 % ) " "Info: Total interconnect delay = 1.054 ns ( 36.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { Clk Clk~clkctrl dff_A } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { Clk {} Clk~combout {} Clk~clkctrl {} dff_A {} } { 0.000ns 0.000ns 0.139ns 0.915ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.660 ns" { Sw_n[0] dff_A } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.660 ns" { Sw_n[0] {} Sw_n[0]~combout {} dff_A {} } { 0.000ns 0.000ns 6.206ns } { 0.000ns 0.994ns 0.460ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.860 ns" { Clk Clk~clkctrl dff_A } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.860 ns" { Clk {} Clk~combout {} Clk~clkctrl {} dff_A {} } { 0.000ns 0.000ns 0.139ns 0.915ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Sev_Seg_Led_Data_n\[7\] Cout\[22\] 9.409 ns register " "Info: tco from clock \"Clk\" to destination pin \"Sev_Seg_Led_Data_n\[7\]\" through register \"Cout\[22\]\" is 9.409 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 4.091 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 4.091 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.285 ns) + CELL(0.666 ns) 4.091 ns Cout\[22\] 2 REG LCFF_X2_Y16_N21 3 " "Info: 2: + IC(2.285 ns) + CELL(0.666 ns) = 4.091 ns; Loc. = LCFF_X2_Y16_N21; Fanout = 3; REG Node = 'Cout\[22\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.951 ns" { Clk Cout[22] } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 44.15 % ) " "Info: Total cell delay = 1.806 ns ( 44.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.285 ns ( 55.85 % ) " "Info: Total interconnect delay = 2.285 ns ( 55.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.091 ns" { Clk Cout[22] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.091 ns" { Clk {} Clk~combout {} Cout[22] {} } { 0.000ns 0.000ns 2.285ns } { 0.000ns 1.140ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.014 ns + Longest register pin " "Info: + Longest register to pin delay is 5.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[22\] 1 REG LCFF_X2_Y16_N21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y16_N21; Fanout = 3; REG Node = 'Cout\[22\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[22] } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.460 ns) + CELL(0.370 ns) 0.830 ns Sev_Seg_Led_Data_n~16 2 COMB LCCOMB_X2_Y16_N22 1 " "Info: 2: + IC(0.460 ns) + CELL(0.370 ns) = 0.830 ns; Loc. = LCCOMB_X2_Y16_N22; Fanout = 1; COMB Node = 'Sev_Seg_Led_Data_n~16'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.830 ns" { Cout[22] Sev_Seg_Led_Data_n~16 } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(3.276 ns) 5.014 ns Sev_Seg_Led_Data_n\[7\] 3 PIN PIN_205 0 " "Info: 3: + IC(0.908 ns) + CELL(3.276 ns) = 5.014 ns; Loc. = PIN_205; Fanout = 0; PIN Node = 'Sev_Seg_Led_Data_n\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.184 ns" { Sev_Seg_Led_Data_n~16 Sev_Seg_Led_Data_n[7] } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.646 ns ( 72.72 % ) " "Info: Total cell delay = 3.646 ns ( 72.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.368 ns ( 27.28 % ) " "Info: Total interconnect delay = 1.368 ns ( 27.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.014 ns" { Cout[22] Sev_Seg_Led_Data_n~16 Sev_Seg_Led_Data_n[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.014 ns" { Cout[22] {} Sev_Seg_Led_Data_n~16 {} Sev_Seg_Led_Data_n[7] {} } { 0.000ns 0.460ns 0.908ns } { 0.000ns 0.370ns 3.276ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.091 ns" { Clk Cout[22] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.091 ns" { Clk {} Clk~combout {} Cout[22] {} } { 0.000ns 0.000ns 2.285ns } { 0.000ns 1.140ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.014 ns" { Cout[22] Sev_Seg_Led_Data_n~16 Sev_Seg_Led_Data_n[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.014 ns" { Cout[22] {} Sev_Seg_Led_Data_n~16 {} Sev_Seg_Led_Data_n[7] {} } { 0.000ns 0.460ns 0.908ns } { 0.000ns 0.370ns 3.276ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}