prev_cmp_timer.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 22:12:52 2008 " "Info: Processing started: Wed Jul 02 22:12:52 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Timer -c Timer " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Timer -c Timer" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Peak virtual memory: 152 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 22:12:55 2008 " "Info: Processing ended: Wed Jul 02 22:12:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 22:12:56 2008 " "Info: Processing started: Wed Jul 02 22:12:56 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Timer -c Timer --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Timer -c Timer --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Cout\[22\] " "Info: Detected ripple clock \"Cout\[22\]\" as buffer" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 45 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Cout\[22\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register Timer_Cout:Timer_Cout_A\|hour_L\[2\] register Timer_Disp:Timer_Disp_A\|decorder_sel\[2\] 176.09 MHz 5.679 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 176.09 MHz between source register \"Timer_Cout:Timer_Cout_A\|hour_L\[2\]\" and destination register \"Timer_Disp:Timer_Disp_A\|decorder_sel\[2\]\" (period= 5.679 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.830 ns + Longest register register " "Info: + Longest register to register delay is 1.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Timer_Cout:Timer_Cout_A\|hour_L\[2\] 1 REG LCFF_X28_Y14_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y14_N1; Fanout = 5; REG Node = 'Timer_Cout:Timer_Cout_A\|hour_L\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Timer_Cout:Timer_Cout_A|hour_L[2] } "NODE_NAME" } } { "Timer_Cout.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Cout.v" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.366 ns) 1.140 ns Timer_Disp:Timer_Disp_A\|Mux1~82 2 COMB LCCOMB_X28_Y14_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.366 ns) = 1.140 ns; Loc. = LCCOMB_X28_Y14_N2; Fanout = 1; COMB Node = 'Timer_Disp:Timer_Disp_A\|Mux1~82'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.140 ns" { Timer_Cout:Timer_Cout_A|hour_L[2] Timer_Disp:Timer_Disp_A|Mux1~82 } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.206 ns) 1.722 ns Timer_Disp:Timer_Disp_A\|Mux1~83 3 COMB LCCOMB_X28_Y14_N12 1 " "Info: 3: + IC(0.376 ns) + CELL(0.206 ns) = 1.722 ns; Loc. = LCCOMB_X28_Y14_N12; Fanout = 1; COMB Node = 'Timer_Disp:Timer_Disp_A\|Mux1~83'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.582 ns" { Timer_Disp:Timer_Disp_A|Mux1~82 Timer_Disp:Timer_Disp_A|Mux1~83 } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.830 ns Timer_Disp:Timer_Disp_A\|decorder_sel\[2\] 4 REG LCFF_X28_Y14_N13 7 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.830 ns; Loc. = LCFF_X28_Y14_N13; Fanout = 7; REG Node = 'Timer_Disp:Timer_Disp_A\|decorder_sel\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Timer_Disp:Timer_Disp_A|Mux1~83 Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.680 ns ( 37.16 % ) " "Info: Total cell delay = 0.680 ns ( 37.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.150 ns ( 62.84 % ) " "Info: Total interconnect delay = 1.150 ns ( 62.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.830 ns" { Timer_Cout:Timer_Cout_A|hour_L[2] Timer_Disp:Timer_Disp_A|Mux1~82 Timer_Disp:Timer_Disp_A|Mux1~83 Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.830 ns" { Timer_Cout:Timer_Cout_A|hour_L[2] {} Timer_Disp:Timer_Disp_A|Mux1~82 {} Timer_Disp:Timer_Disp_A|Mux1~83 {} Timer_Disp:Timer_Disp_A|decorder_sel[2] {} } { 0.000ns 0.774ns 0.376ns 0.000ns } { 0.000ns 0.366ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.585 ns - Smallest " "Info: - Smallest clock skew is -3.585 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.861 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 2.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'Clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.666 ns) 2.861 ns Timer_Disp:Timer_Disp_A\|decorder_sel\[2\] 3 REG LCFF_X28_Y14_N13 7 " "Info: 3: + IC(0.916 ns) + CELL(0.666 ns) = 2.861 ns; Loc. = LCFF_X28_Y14_N13; Fanout = 7; REG Node = 'Timer_Disp:Timer_Disp_A\|decorder_sel\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { Clk~clkctrl Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.12 % ) " "Info: Total cell delay = 1.806 ns ( 63.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.055 ns ( 36.88 % ) " "Info: Total interconnect delay = 1.055 ns ( 36.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { Clk Clk~clkctrl Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Timer_Disp:Timer_Disp_A|decorder_sel[2] {} } { 0.000ns 0.000ns 0.139ns 0.916ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 6.446 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 6.446 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.253 ns) + CELL(0.970 ns) 3.363 ns Cout\[22\] 2 REG LCFF_X1_Y14_N21 3 " "Info: 2: + IC(1.253 ns) + CELL(0.970 ns) = 3.363 ns; Loc. = LCFF_X1_Y14_N21; Fanout = 3; REG Node = 'Cout\[22\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.223 ns" { Clk Cout[22] } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.000 ns) 4.864 ns Cout\[22\]~clkctrl 3 COMB CLKCTRL_G3 13 " "Info: 3: + IC(1.501 ns) + CELL(0.000 ns) = 4.864 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'Cout\[22\]~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { Cout[22] Cout[22]~clkctrl } "NODE_NAME" } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.666 ns) 6.446 ns Timer_Cout:Timer_Cout_A\|hour_L\[2\] 4 REG LCFF_X28_Y14_N1 5 " "Info: 4: + IC(0.916 ns) + CELL(0.666 ns) = 6.446 ns; Loc. = LCFF_X28_Y14_N1; Fanout = 5; REG Node = 'Timer_Cout:Timer_Cout_A\|hour_L\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { Cout[22]~clkctrl Timer_Cout:Timer_Cout_A|hour_L[2] } "NODE_NAME" } } { "Timer_Cout.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Cout.v" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 43.07 % ) " "Info: Total cell delay = 2.776 ns ( 43.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.670 ns ( 56.93 % ) " "Info: Total interconnect delay = 3.670 ns ( 56.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.446 ns" { Clk Cout[22] Cout[22]~clkctrl Timer_Cout:Timer_Cout_A|hour_L[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.446 ns" { Clk {} Clk~combout {} Cout[22] {} Cout[22]~clkctrl {} Timer_Cout:Timer_Cout_A|hour_L[2] {} } { 0.000ns 0.000ns 1.253ns 1.501ns 0.916ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/