prev_cmp_timer.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 22:12:37 2008 " "Info: Processing started: Wed Jul 02 22:12:37 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Timer -c Timer " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Timer -c Timer" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Timer.v 3 3 " "Warning: Using design file Timer.v, which is not specified as a design file for the current project, but contains definitions for 3 design units and 3 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Timer_Cout " "Info: Found entity 1: Timer_Cout" {  } { { "Timer_Cout.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Cout.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 Timer_Disp " "Info: Found entity 2: Timer_Disp" {  } { { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 Timer " "Info: Found entity 3: Timer" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Timer " "Info: Elaborating entity \"Timer\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Timer_Cout Timer_Cout:Timer_Cout_A " "Info: Elaborating entity \"Timer_Cout\" for hierarchy \"Timer_Cout:Timer_Cout_A\"" {  } { { "Timer.v" "Timer_Cout_A" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 63 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Timer_Disp Timer_Disp:Timer_Disp_A " "Info: Elaborating entity \"Timer_Disp\" for hierarchy \"Timer_Disp:Timer_Disp_A\"" {  } { { "Timer.v" "Timer_Disp_A" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "Led_En_n VCC " "Warning (13410): Pin \"Led_En_n\" is stuck at VCC" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "18 18 " "Info: 18 registers lost all their fanouts during netlist optimizations. The first 18 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[23\] " "Info: Register \"Cout\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[24\] " "Info: Register \"Cout\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[25\] " "Info: Register \"Cout\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[15\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[16\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[17\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[18\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[19\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[20\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[21\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[22\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[23\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[23\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[24\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[24\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[25\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[25\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[26\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[26\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[27\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[27\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[28\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[28\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Timer_Disp:Timer_Disp_A\|count\[29\] " "Info: Register \"Timer_Disp:Timer_Disp_A\|count\[29\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Sw_n\[1\] " "Warning (15610): No output dependent on input pin \"Sw_n\[1\]\"" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 14 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Sw_n\[2\] " "Warning (15610): No output dependent on input pin \"Sw_n\[2\]\"" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 14 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Sw_n\[3\] " "Warning (15610): No output dependent on input pin \"Sw_n\[3\]\"" {  } { { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 14 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "97 " "Info: Implemented 97 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "79 " "Info: Implemented 79 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "158 " "Info: Peak virtual memory: 158 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 22:12:41 2008 " "Info: Processing ended: Wed Jul 02 22:12:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 22:12:43 2008 " "Info: Processing started: Wed Jul 02 22:12:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}