timer.fit.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.104 ns register register " "Info: Estimated most critical path is register to register delay of 2.104 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Timer_Cout:Timer_Cout_A\|min_L\[2\] 1 REG LAB_X29_Y14 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X29_Y14; Fanout = 5; REG Node = 'Timer_Cout:Timer_Cout_A\|min_L\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Timer_Cout:Timer_Cout_A|min_L[2] } "NODE_NAME" } } { "Timer_Cout.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Cout.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.650 ns) 1.186 ns Timer_Disp:Timer_Disp_A\|Mux1~82 2 COMB LAB_X30_Y14 1 " "Info: 2: + IC(0.536 ns) + CELL(0.650 ns) = 1.186 ns; Loc. = LAB_X30_Y14; Fanout = 1; COMB Node = 'Timer_Disp:Timer_Disp_A\|Mux1~82'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.186 ns" { Timer_Cout:Timer_Cout_A|min_L[2] Timer_Disp:Timer_Disp_A|Mux1~82 } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.650 ns) 1.996 ns Timer_Disp:Timer_Disp_A\|Mux1~83 3 COMB LAB_X30_Y14 1 " "Info: 3: + IC(0.160 ns) + CELL(0.650 ns) = 1.996 ns; Loc. = LAB_X30_Y14; Fanout = 1; COMB Node = 'Timer_Disp:Timer_Disp_A\|Mux1~83'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { Timer_Disp:Timer_Disp_A|Mux1~82 Timer_Disp:Timer_Disp_A|Mux1~83 } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.104 ns Timer_Disp:Timer_Disp_A\|decorder_sel\[2\] 4 REG LAB_X30_Y14 7 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.104 ns; Loc. = LAB_X30_Y14; Fanout = 7; REG Node = 'Timer_Disp:Timer_Disp_A\|decorder_sel\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Timer_Disp:Timer_Disp_A|Mux1~83 Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } } { "Timer_Disp.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer_Disp.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.408 ns ( 66.92 % ) " "Info: Total cell delay = 1.408 ns ( 66.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.696 ns ( 33.08 % ) " "Info: Total interconnect delay = 0.696 ns ( 33.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.104 ns" { Timer_Cout:Timer_Cout_A|min_L[2] Timer_Disp:Timer_Disp_A|Mux1~82 Timer_Disp:Timer_Disp_A|Mux1~83 Timer_Disp:Timer_Disp_A|decorder_sel[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X10_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "13 " "Warning: Found 13 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Sel_n\[0\] 0 " "Info: Pin \"Sev_Seg_Led_Sel_n\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Sel_n\[1\] 0 " "Info: Pin \"Sev_Seg_Led_Sel_n\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Sel_n\[2\] 0 " "Info: Pin \"Sev_Seg_Led_Sel_n\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Sel_n\[3\] 0 " "Info: Pin \"Sev_Seg_Led_Sel_n\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Data_n\[0\] 0 " "Info: Pin \"Sev_Seg_Led_Data_n\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Data_n\[1\] 0 " "Info: Pin \"Sev_Seg_Led_Data_n\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Data_n\[2\] 0 " "Info: Pin \"Sev_Seg_Led_Data_n\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Data_n\[3\] 0 " "Info: Pin \"Sev_Seg_Led_Data_n\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Data_n\[4\] 0 " "Info: Pin \"Sev_Seg_Led_Data_n\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Data_n\[5\] 0 " "Info: Pin \"Sev_Seg_Led_Data_n\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Data_n\[6\] 0 " "Info: Pin \"Sev_Seg_Led_Data_n\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Data_n\[7\] 0 " "Info: Pin \"Sev_Seg_Led_Data_n\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led_En_n 0 " "Info: Pin \"Led_En_n\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Led_En_n VCC " "Info: Pin Led_En_n has VCC driving its datain port" {  } { { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { Led_En_n } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Led_En_n" } } } } { "Timer.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.v" 19 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Led_En_n } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.fit.smsg " "Info: Generated suppressed messages file F:/FPGA4U/Example/FPGA4U/Timer/Timer/Timer.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 39 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 39 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "186 " "Info: Peak virtual memory: 186 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 22:13:44 2008 " "Info: Processing ended: Wed Jul 02 22:13:44 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}