timer_disp.v

来自「采用Altera公司的CycloneII芯片EP2C8的一些程序代码。」· Verilog 代码 · 共 75 行

module Timer_Disp(
					clk,

					hour_H,
					hour_L,
					min_H,
					min_L,
					
					
					led_com_n,
					led_data					
				);
					

input [1:0] hour_H;
input [3:0] hour_L;
input [2:0] min_H;
input [3:0] min_L;
input clk;
output [6:0] led_data;
output [3:0] led_com_n;

reg [29:0] count;
reg [3:0] decorder_sel;
reg [6:0] led_data;
reg [3:0] led_com_n;

/*--------------------------------------------------------------------------*/

		always @(posedge clk)
			begin
				count <= count + 30'd1;
			end

/*--------------------------------------------------------------------------*/
			
		always @(posedge clk)					
			begin
				case (count[14:13])					
					2'd0: decorder_sel <= hour_H;	 	
					2'd1: decorder_sel <= hour_L;		
					2'd2: decorder_sel <= min_H;		
					2'd3: decorder_sel <= min_L;		
				endcase

				case (count[14:13])					
					2'h0: led_com_n <= 4'b1110;		
					2'h1: led_com_n <= 4'b1101;		
					2'h2: led_com_n <= 4'b1011;		
					2'h3: led_com_n <= 4'b0111;		
				endcase
			end
			
/*--------------------------------------------------------------------------*/
			
		always@(posedge clk)
			begin
				case(decorder_sel)
					4'b0000 : led_data = 7'b1000000;
					4'b0001 : led_data = 7'b1111001;
					4'b0010 : led_data = 7'b0100100;
					4'b0011 : led_data = 7'b0110000;
					4'b0100 : led_data = 7'b0011001;
					4'b0101 : led_data = 7'b0010010;
					4'b0110 : led_data = 7'b0000010;
					4'b0111 : led_data = 7'b1111000;
					4'b1000 : led_data = 7'b0000000;
					4'b1001 : led_data = 7'b0011000;				
					default   led_data = 7'b1000000;
				endcase
		end
		
/*--------------------------------------------------------------------------*/
		
endmodule