timer.tan.rpt

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clk'                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                    ; To                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 145.73 MHz ( period = 6.862 ns )                    ; Timer_Cout:Timer_Cout_A|min_L[2]        ; Timer_Disp:Timer_Disp_A|decorder_sel[2] ; Clk        ; Clk      ; None                        ; None                      ; 1.641 ns                ;
; N/A                                     ; 145.92 MHz ( period = 6.853 ns )                    ; Timer_Cout:Timer_Cout_A|min_H[0]        ; Timer_Disp:Timer_Disp_A|decorder_sel[0] ; Clk        ; Clk      ; None                        ; None                      ; 1.632 ns                ;
; N/A                                     ; 147.56 MHz ( period = 6.777 ns )                    ; Timer_Cout:Timer_Cout_A|min_H[1]        ; Timer_Disp:Timer_Disp_A|decorder_sel[1] ; Clk        ; Clk      ; None                        ; None                      ; 1.556 ns                ;
; N/A                                     ; 147.75 MHz ( period = 6.768 ns )                    ; Timer_Cout:Timer_Cout_A|hour_H[0]       ; Timer_Disp:Timer_Disp_A|decorder_sel[0] ; Clk        ; Clk      ; None                        ; None                      ; 1.547 ns                ;
; N/A                                     ; 147.97 MHz ( period = 6.758 ns )                    ; Timer_Cout:Timer_Cout_A|hour_H[1]       ; Timer_Disp:Timer_Disp_A|decorder_sel[1] ; Clk        ; Clk      ; None                        ; None                      ; 1.537 ns                ;
; N/A                                     ; 148.08 MHz ( period = 6.753 ns )                    ; Timer_Cout:Timer_Cout_A|hour_L[3]       ; Timer_Disp:Timer_Disp_A|decorder_sel[3] ; Clk        ; Clk      ; None                        ; None                      ; 1.532 ns                ;
; N/A                                     ; 148.19 MHz ( period = 6.748 ns )                    ; Timer_Cout:Timer_Cout_A|hour_L[2]       ; Timer_Disp:Timer_Disp_A|decorder_sel[2] ; Clk        ; Clk      ; None                        ; None                      ; 1.527 ns                ;
; N/A                                     ; 148.41 MHz ( period = 6.738 ns )                    ; Timer_Cout:Timer_Cout_A|hour_L[1]       ; Timer_Disp:Timer_Disp_A|decorder_sel[1] ; Clk        ; Clk      ; None                        ; None                      ; 1.517 ns                ;
; N/A                                     ; 148.59 MHz ( period = 6.730 ns )                    ; Timer_Cout:Timer_Cout_A|min_L[0]        ; Timer_Disp:Timer_Disp_A|decorder_sel[0] ; Clk        ; Clk      ; None                        ; None                      ; 1.509 ns                ;
; N/A                                     ; 148.65 MHz ( period = 6.727 ns )                    ; Timer_Cout:Timer_Cout_A|min_L[1]        ; Timer_Disp:Timer_Disp_A|decorder_sel[1] ; Clk        ; Clk      ; None                        ; None                      ; 1.506 ns                ;
; N/A                                     ; 154.73 MHz ( period = 6.463 ns )                    ; Timer_Cout:Timer_Cout_A|hour_L[0]       ; Timer_Disp:Timer_Disp_A|decorder_sel[0] ; Clk        ; Clk      ; None                        ; None                      ; 1.236 ns                ;
; N/A                                     ; 155.11 MHz ( period = 6.447 ns )                    ; Timer_Cout:Timer_Cout_A|min_H[2]        ; Timer_Disp:Timer_Disp_A|decorder_sel[2] ; Clk        ; Clk      ; None                        ; None                      ; 1.226 ns                ;
; N/A                                     ; 159.57 MHz ( period = 6.267 ns )                    ; Timer_Cout:Timer_Cout_A|min_L[3]        ; Timer_Disp:Timer_Disp_A|decorder_sel[3] ; Clk        ; Clk      ; None                        ; None                      ; 1.046 ns                ;
; N/A                                     ; 214.78 MHz ( period = 4.656 ns )                    ; Timer_Cout:Timer_Cout_A|hour_L[0]       ; Timer_Cout:Timer_Cout_A|hour_H[1]       ; Clk        ; Clk      ; None                        ; None                      ; 4.386 ns                ;
; N/A                                     ; 231.21 MHz ( period = 4.325 ns )                    ; Timer_Cout:Timer_Cout_A|min_L[2]        ; Timer_Cout:Timer_Cout_A|hour_L[0]       ; Clk        ; Clk      ; None                        ; None                      ; 4.067 ns                ;
; N/A                                     ; 238.21 MHz ( period = 4.198 ns )                    ; Timer_Disp:Timer_Disp_A|decorder_sel[3] ; Timer_Disp:Timer_Disp_A|led_data[6]     ; Clk        ; Clk      ; None                        ; None                      ; 3.937 ns                ;
; N/A                                     ; 239.23 MHz ( period = 4.180 ns )                    ; Timer_Cout:Timer_Cout_A|hour_L[3]       ; Timer_Cout:Timer_Cout_A|hour_H[1]       ; Clk        ; Clk      ; None                        ; None                      ; 3.916 ns                ;
; N/A                                     ; 240.79 MHz ( period = 4.153 ns )                    ; Timer_Disp:Timer_Disp_A|decorder_sel[3] ; Timer_Disp:Timer_Disp_A|led_data[4]     ; Clk        ; Clk      ; None                        ; None                      ; 3.892 ns                ;
; N/A                                     ; 240.91 MHz ( period = 4.151 ns )                    ; Timer_Disp:Timer_Disp_A|decorder_sel[3] ; Timer_Disp:Timer_Disp_A|led_data[3]     ; Clk        ; Clk      ; None                        ; None                      ; 3.890 ns                ;