📄 timer.tan.rpt
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Classic Timing Analyzer report for Timer
Wed Jul 02 22:13:49 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'Clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------+-----------------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------+-----------------------------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.760 ns ; Sw_n[0] ; dff_A ; -- ; Clk ; 0 ;
; Worst-case tco ; N/A ; None ; 9.409 ns ; Cout[22] ; Sev_Seg_Led_Data_n[7] ; Clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -4.494 ns ; Sw_n[0] ; dff_A ; -- ; Clk ; 0 ;
; Clock Setup: 'Clk' ; N/A ; None ; 145.73 MHz ( period = 6.862 ns ) ; Timer_Cout:Timer_Cout_A|min_L[2] ; Timer_Disp:Timer_Disp_A|decorder_sel[2] ; Clk ; Clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------+-----------------------------------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8Q208C8 ; ; ; ;
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