prev_cmp_segment1.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 21:56:14 2008 " "Info: Processing started: Wed Jul 02 21:56:14 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Segment1 -c Segment1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Segment1 -c Segment1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Segment1.v 1 1 " "Warning: Using design file Segment1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Segment1 " "Info: Found entity 1: Segment1" {  } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Segment1 " "Info: Elaborating entity \"Segment1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Sev_Seg_Led_Data_n\[7\]~reg0 data_in GND " "Warning (14130): Reduced register \"Sev_Seg_Led_Data_n\[7\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Sel_n\[0\] GND " "Warning (13410): Pin \"Sev_Seg_Led_Sel_n\[0\]\" is stuck at GND" {  } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 11 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Sel_n\[1\] GND " "Warning (13410): Pin \"Sev_Seg_Led_Sel_n\[1\]\" is stuck at GND" {  } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 11 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Sel_n\[2\] GND " "Warning (13410): Pin \"Sev_Seg_Led_Sel_n\[2\]\" is stuck at GND" {  } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 11 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Sel_n\[3\] GND " "Warning (13410): Pin \"Sev_Seg_Led_Sel_n\[3\]\" is stuck at GND" {  } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 11 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Data_n\[7\] GND " "Warning (13410): Pin \"Sev_Seg_Led_Data_n\[7\]\" is stuck at GND" {  } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Led_En_n VCC " "Warning (13410): Pin \"Led_En_n\" is stuck at VCC" {  } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 14 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Buzz GND " "Warning (13410): Pin \"Buzz\" is stuck at GND" {  } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 15 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "56 " "Info: Implemented 56 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "41 " "Info: Implemented 41 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Peak virtual memory: 156 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 21:56:16 2008 " "Info: Processing ended: Wed Jul 02 21:56:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}