📄 prev_cmp_segment1.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" { } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register Cout\[0\] register Cout\[29\] 204.62 MHz 4.887 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 204.62 MHz between source register \"Cout\[0\]\" and destination register \"Cout\[29\]\" (period= 4.887 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.607 ns + Longest register register " "Info: + Longest register to register delay is 4.607 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[0\] 1 REG LCFF_X14_Y14_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y14_N1; Fanout = 3; REG Node = 'Cout\[0\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[0] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.753 ns) + CELL(0.621 ns) 1.374 ns Cout\[1\]~177 2 COMB LCCOMB_X14_Y14_N4 2 " "Info: 2: + IC(0.753 ns) + CELL(0.621 ns) = 1.374 ns; Loc. = LCCOMB_X14_Y14_N4; Fanout = 2; COMB Node = 'Cout\[1\]~177'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.374 ns" { Cout[0] Cout[1]~177 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.460 ns Cout\[2\]~179 3 COMB LCCOMB_X14_Y14_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.460 ns; Loc. = LCCOMB_X14_Y14_N6; Fanout = 2; COMB Node = 'Cout\[2\]~179'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[1]~177 Cout[2]~179 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.546 ns Cout\[3\]~181 4 COMB LCCOMB_X14_Y14_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.546 ns; Loc. = LCCOMB_X14_Y14_N8; Fanout = 2; COMB Node = 'Cout\[3\]~181'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[2]~179 Cout[3]~181 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.632 ns Cout\[4\]~183 5 COMB LCCOMB_X14_Y14_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.632 ns; Loc. = LCCOMB_X14_Y14_N10; Fanout = 2; COMB Node = 'Cout\[4\]~183'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[3]~181 Cout[4]~183 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.718 ns Cout\[5\]~185 6 COMB LCCOMB_X14_Y14_N12 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.718 ns; Loc. = LCCOMB_X14_Y14_N12; Fanout = 2; COMB Node = 'Cout\[5\]~185'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[4]~183 Cout[5]~185 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.908 ns Cout\[6\]~187 7 COMB LCCOMB_X14_Y14_N14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.190 ns) = 1.908 ns; Loc. = LCCOMB_X14_Y14_N14; Fanout = 2; COMB Node = 'Cout\[6\]~187'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Cout[5]~185 Cout[6]~187 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.994 ns Cout\[7\]~189 8 COMB LCCOMB_X14_Y14_N16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.994 ns; Loc. = LCCOMB_X14_Y14_N16; Fanout = 2; COMB Node = 'Cout\[7\]~189'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[6]~187 Cout[7]~189 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.080 ns Cout\[8\]~191 9 COMB LCCOMB_X14_Y14_N18 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.080 ns; Loc. = LCCOMB_X14_Y14_N18; Fanout = 2; COMB Node = 'Cout\[8\]~191'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[7]~189 Cout[8]~191 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.166 ns Cout\[9\]~193 10 COMB LCCOMB_X14_Y14_N20 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.166 ns; Loc. = LCCOMB_X14_Y14_N20; Fanout = 2; COMB Node = 'Cout\[9\]~193'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[8]~191 Cout[9]~193 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.252 ns Cout\[10\]~195 11 COMB LCCOMB_X14_Y14_N22 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.252 ns; Loc. = LCCOMB_X14_Y14_N22; Fanout = 2; COMB Node = 'Cout\[10\]~195'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[9]~193 Cout[10]~195 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.338 ns Cout\[11\]~197 12 COMB LCCOMB_X14_Y14_N24 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.338 ns; Loc. = LCCOMB_X14_Y14_N24; Fanout = 2; COMB Node = 'Cout\[11\]~197'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[10]~195 Cout[11]~197 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.424 ns Cout\[12\]~199 13 COMB LCCOMB_X14_Y14_N26 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.424 ns; Loc. = LCCOMB_X14_Y14_N26; Fanout = 2; COMB Node = 'Cout\[12\]~199'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[11]~197 Cout[12]~199 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.510 ns Cout\[13\]~201 14 COMB LCCOMB_X14_Y14_N28 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.510 ns; Loc. = LCCOMB_X14_Y14_N28; Fanout = 2; COMB Node = 'Cout\[13\]~201'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[12]~199 Cout[13]~201 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 2.685 ns Cout\[14\]~203 15 COMB LCCOMB_X14_Y14_N30 2 " "Info: 15: + IC(0.000 ns) + CELL(0.175 ns) = 2.685 ns; Loc. = LCCOMB_X14_Y14_N30; Fanout = 2; COMB Node = 'Cout\[14\]~203'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.175 ns" { Cout[13]~201 Cout[14]~203 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.771 ns Cout\[15\]~205 16 COMB LCCOMB_X14_Y13_N0 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.771 ns; Loc. = LCCOMB_X14_Y13_N0; Fanout = 2; COMB Node = 'Cout\[15\]~205'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[14]~203 Cout[15]~205 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.857 ns Cout\[16\]~207 17 COMB LCCOMB_X14_Y13_N2 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.857 ns; Loc. = LCCOMB_X14_Y13_N2; Fanout = 2; COMB Node = 'Cout\[16\]~207'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[15]~205 Cout[16]~207 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.943 ns Cout\[17\]~209 18 COMB LCCOMB_X14_Y13_N4 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.943 ns; Loc. = LCCOMB_X14_Y13_N4; Fanout = 2; COMB Node = 'Cout\[17\]~209'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[16]~207 Cout[17]~209 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.029 ns Cout\[18\]~211 19 COMB LCCOMB_X14_Y13_N6 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.029 ns; Loc. = LCCOMB_X14_Y13_N6; Fanout = 2; COMB Node = 'Cout\[18\]~211'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[17]~209 Cout[18]~211 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.115 ns Cout\[19\]~213 20 COMB LCCOMB_X14_Y13_N8 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.115 ns; Loc. = LCCOMB_X14_Y13_N8; Fanout = 2; COMB Node = 'Cout\[19\]~213'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[18]~211 Cout[19]~213 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.201 ns Cout\[20\]~215 21 COMB LCCOMB_X14_Y13_N10 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.201 ns; Loc. = LCCOMB_X14_Y13_N10; Fanout = 2; COMB Node = 'Cout\[20\]~215'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[19]~213 Cout[20]~215 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.287 ns Cout\[21\]~217 22 COMB LCCOMB_X14_Y13_N12 2 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.287 ns; Loc. = LCCOMB_X14_Y13_N12; Fanout = 2; COMB Node = 'Cout\[21\]~217'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[20]~215 Cout[21]~217 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 3.477 ns Cout\[22\]~219 23 COMB LCCOMB_X14_Y13_N14 2 " "Info: 23: + IC(0.000 ns) + CELL(0.190 ns) = 3.477 ns; Loc. = LCCOMB_X14_Y13_N14; Fanout = 2; COMB Node = 'Cout\[22\]~219'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Cout[21]~217 Cout[22]~219 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.563 ns Cout\[23\]~221 24 COMB LCCOMB_X14_Y13_N16 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.563 ns; Loc. = LCCOMB_X14_Y13_N16; Fanout = 2; COMB Node = 'Cout\[23\]~221'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[22]~219 Cout[23]~221 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.649 ns Cout\[24\]~223 25 COMB LCCOMB_X14_Y13_N18 2 " "Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.649 ns; Loc. = LCCOMB_X14_Y13_N18; Fanout = 2; COMB Node = 'Cout\[24\]~223'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[23]~221 Cout[24]~223 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.735 ns Cout\[25\]~225 26 COMB LCCOMB_X14_Y13_N20 2 " "Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.735 ns; Loc. = LCCOMB_X14_Y13_N20; Fanout = 2; COMB Node = 'Cout\[25\]~225'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[24]~223 Cout[25]~225 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.821 ns Cout\[26\]~227 27 COMB LCCOMB_X14_Y13_N22 2 " "Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.821 ns; Loc. = LCCOMB_X14_Y13_N22; Fanout = 2; COMB Node = 'Cout\[26\]~227'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[25]~225 Cout[26]~227 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.907 ns Cout\[27\]~229 28 COMB LCCOMB_X14_Y13_N24 2 " "Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.907 ns; Loc. = LCCOMB_X14_Y13_N24; Fanout = 2; COMB Node = 'Cout\[27\]~229'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[26]~227 Cout[27]~229 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.993 ns Cout\[28\]~231 29 COMB LCCOMB_X14_Y13_N26 1 " "Info: 29: + IC(0.000 ns) + CELL(0.086 ns) = 3.993 ns; Loc. = LCCOMB_X14_Y13_N26; Fanout = 1; COMB Node = 'Cout\[28\]~231'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[27]~229 Cout[28]~231 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.499 ns Cout\[29\]~232 30 COMB LCCOMB_X14_Y13_N28 1 " "Info: 30: + IC(0.000 ns) + CELL(0.506 ns) = 4.499 ns; Loc. = LCCOMB_X14_Y13_N28; Fanout = 1; COMB Node = 'Cout\[29\]~232'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Cout[28]~231 Cout[29]~232 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.607 ns Cout\[29\] 31 REG LCFF_X14_Y13_N29 2 " "Info: 31: + IC(0.000 ns) + CELL(0.108 ns) = 4.607 ns; Loc. = LCFF_X14_Y13_N29; Fanout = 2; REG Node = 'Cout\[29\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Cout[29]~232 Cout[29] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.854 ns ( 83.66 % ) " "Info: Total cell delay = 3.854 ns ( 83.66 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.753 ns ( 16.34 % ) " "Info: Total interconnect delay = 0.753 ns ( 16.34 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.607 ns" { Cout[0] Cout[1]~177 Cout[2]~179 Cout[3]~181 Cout[4]~183 Cout[5]~185 Cout[6]~187 Cout[7]~189 Cout[8]~191 Cout[9]~193 Cout[10]~195 Cout[11]~197 Cout[12]~199 Cout[13]~201 Cout[14]~203 Cout[15]~205 Cout[16]~207 Cout[17]~209 Cout[18]~211 Cout[19]~213 Cout[20]~215 Cout[21]~217 Cout[22]~219 Cout[23]~221 Cout[24]~223 Cout[25]~225 Cout[26]~227 Cout[27]~229 Cout[28]~231 Cout[29]~232 Cout[29] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.607 ns" { Cout[0] {} Cout[1]~177 {} Cout[2]~179 {} Cout[3]~181 {} Cout[4]~183 {} Cout[5]~185 {} Cout[6]~187 {} Cout[7]~189 {} Cout[8]~191 {} Cout[9]~193 {} Cout[10]~195 {} Cout[11]~197 {} Cout[12]~199 {} Cout[13]~201 {} Cout[14]~203 {} Cout[15]~205 {} Cout[16]~207 {} Cout[17]~209 {} Cout[18]~211 {} Cout[19]~213 {} Cout[20]~215 {} Cout[21]~217 {} Cout[22]~219 {} Cout[23]~221 {} Cout[24]~223 {} Cout[25]~225 {} Cout[26]~227 {} Cout[27]~229 {} Cout[28]~231 {} Cout[29]~232 {} Cout[29] {} } { 0.000ns 0.753ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.016 ns - Smallest " "Info: - Smallest clock skew is -0.016 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.855 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 2.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 41 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 41; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.910 ns) + CELL(0.666 ns) 2.855 ns Cout\[29\] 3 REG LCFF_X14_Y13_N29 2 " "Info: 3: + IC(0.910 ns) + CELL(0.666 ns) = 2.855 ns; Loc. = LCFF_X14_Y13_N29; Fanout = 2; REG Node = 'Cout\[29\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.576 ns" { Clk~clkctrl Cout[29] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.26 % ) " "Info: Total cell delay = 1.806 ns ( 63.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.049 ns ( 36.74 % ) " "Info: Total interconnect delay = 1.049 ns ( 36.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { Clk Clk~clkctrl Cout[29] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[29] {} } { 0.000ns 0.000ns 0.139ns 0.910ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.871 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 2.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 41 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 41; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.666 ns) 2.871 ns Cout\[0\] 3 REG LCFF_X14_Y14_N1 3 " "Info: 3: + IC(0.926 ns) + CELL(0.666 ns) = 2.871 ns; Loc. = LCFF_X14_Y14_N1; Fanout = 3; REG Node = 'Cout\[0\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { Clk~clkctrl Cout[0] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.90 % ) " "Info: Total cell delay = 1.806 ns ( 62.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 37.10 % ) " "Info: Total interconnect delay = 1.065 ns ( 37.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { Clk Clk~clkctrl Cout[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.871 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[0] {} } { 0.000ns 0.000ns 0.139ns 0.926ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { Clk Clk~clkctrl Cout[29] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[29] {} } { 0.000ns 0.000ns 0.139ns 0.910ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { Clk Clk~clkctrl Cout[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.871 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[0] {} } { 0.000ns 0.000ns 0.139ns 0.926ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.607 ns" { Cout[0] Cout[1]~177 Cout[2]~179 Cout[3]~181 Cout[4]~183 Cout[5]~185 Cout[6]~187 Cout[7]~189 Cout[8]~191 Cout[9]~193 Cout[10]~195 Cout[11]~197 Cout[12]~199 Cout[13]~201 Cout[14]~203 Cout[15]~205 Cout[16]~207 Cout[17]~209 Cout[18]~211 Cout[19]~213 Cout[20]~215 Cout[21]~217 Cout[22]~219 Cout[23]~221 Cout[24]~223 Cout[25]~225 Cout[26]~227 Cout[27]~229 Cout[28]~231 Cout[29]~232 Cout[29] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.607 ns" { Cout[0] {} Cout[1]~177 {} Cout[2]~179 {} Cout[3]~181 {} Cout[4]~183 {} Cout[5]~185 {} Cout[6]~187 {} Cout[7]~189 {} Cout[8]~191 {} Cout[9]~193 {} Cout[10]~195 {} Cout[11]~197 {} Cout[12]~199 {} Cout[13]~201 {} Cout[14]~203 {} Cout[15]~205 {} Cout[16]~207 {} Cout[17]~209 {} Cout[18]~211 {} Cout[19]~213 {} Cout[20]~215 {} Cout[21]~217 {} Cout[22]~219 {} Cout[23]~221 {} Cout[24]~223 {} Cout[25]~225 {} Cout[26]~227 {} Cout[27]~229 {} Cout[28]~231 {} Cout[29]~232 {} Cout[29] {} } { 0.000ns 0.753ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { Clk Clk~clkctrl Cout[29] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[29] {} } { 0.000ns 0.000ns 0.139ns 0.910ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { Clk Clk~clkctrl Cout[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.871 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[0] {} } { 0.000ns 0.000ns 0.139ns 0.926ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Sev_Seg_Led_Data_n\[4\] Sev_Seg_Led_Data_n\[4\]~reg0 8.544 ns register " "Info: tco from clock \"Clk\" to destination pin \"Sev_Seg_Led_Data_n\[4\]\" through register \"Sev_Seg_Led_Data_n\[4\]~reg0\" is 8.544 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.850 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 2.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 41 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 41; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.905 ns) + CELL(0.666 ns) 2.850 ns Sev_Seg_Led_Data_n\[4\]~reg0 3 REG LCFF_X10_Y13_N1 1 " "Info: 3: + IC(0.905 ns) + CELL(0.666 ns) = 2.850 ns; Loc. = LCFF_X10_Y13_N1; Fanout = 1; REG Node = 'Sev_Seg_Led_Data_n\[4\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { Clk~clkctrl Sev_Seg_Led_Data_n[4]~reg0 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.37 % ) " "Info: Total cell delay = 1.806 ns ( 63.37 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.044 ns ( 36.63 % ) " "Info: Total interconnect delay = 1.044 ns ( 36.63 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { Clk Clk~clkctrl Sev_Seg_Led_Data_n[4]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.850 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Sev_Seg_Led_Data_n[4]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.905ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.390 ns + Longest register pin " "Info: + Longest register to pin delay is 5.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Sev_Seg_Led_Data_n\[4\]~reg0 1 REG LCFF_X10_Y13_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y13_N1; Fanout = 1; REG Node = 'Sev_Seg_Led_Data_n\[4\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sev_Seg_Led_Data_n[4]~reg0 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.104 ns) + CELL(3.286 ns) 5.390 ns Sev_Seg_Led_Data_n\[4\] 2 PIN PIN_208 0 " "Info: 2: + IC(2.104 ns) + CELL(3.286 ns) = 5.390 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Sev_Seg_Led_Data_n\[4\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 Sev_Seg_Led_Data_n[4] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.286 ns ( 60.96 % ) " "Info: Total cell delay = 3.286 ns ( 60.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.104 ns ( 39.04 % ) " "Info: Total interconnect delay = 2.104 ns ( 39.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 Sev_Seg_Led_Data_n[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 {} Sev_Seg_Led_Data_n[4] {} } { 0.000ns 2.104ns } { 0.000ns 3.286ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { Clk Clk~clkctrl Sev_Seg_Led_Data_n[4]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.850 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Sev_Seg_Led_Data_n[4]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.905ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 Sev_Seg_Led_Data_n[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 {} Sev_Seg_Led_Data_n[4] {} } { 0.000ns 2.104ns } { 0.000ns 3.286ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
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