prev_cmp_segment1.fit.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.314 ns register register " "Info: Estimated most critical path is register to register delay of 4.314 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[0\] 1 REG LAB_X14_Y14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y14; Fanout = 3; REG Node = 'Cout\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[0] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.596 ns) 1.271 ns Cout\[1\]~177 2 COMB LAB_X14_Y14 2 " "Info: 2: + IC(0.675 ns) + CELL(0.596 ns) = 1.271 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[1\]~177'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { Cout[0] Cout[1]~177 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.357 ns Cout\[2\]~179 3 COMB LAB_X14_Y14 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.357 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[2\]~179'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[1]~177 Cout[2]~179 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.443 ns Cout\[3\]~181 4 COMB LAB_X14_Y14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.443 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[3\]~181'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[2]~179 Cout[3]~181 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.529 ns Cout\[4\]~183 5 COMB LAB_X14_Y14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.529 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[4\]~183'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[3]~181 Cout[4]~183 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.615 ns Cout\[5\]~185 6 COMB LAB_X14_Y14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.615 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[5\]~185'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[4]~183 Cout[5]~185 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.701 ns Cout\[6\]~187 7 COMB LAB_X14_Y14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.701 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[6\]~187'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[5]~185 Cout[6]~187 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.787 ns Cout\[7\]~189 8 COMB LAB_X14_Y14 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.787 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[7\]~189'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[6]~187 Cout[7]~189 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.873 ns Cout\[8\]~191 9 COMB LAB_X14_Y14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.873 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[8\]~191'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[7]~189 Cout[8]~191 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.959 ns Cout\[9\]~193 10 COMB LAB_X14_Y14 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.959 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[9\]~193'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[8]~191 Cout[9]~193 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.045 ns Cout\[10\]~195 11 COMB LAB_X14_Y14 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.045 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[10\]~195'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[9]~193 Cout[10]~195 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.131 ns Cout\[11\]~197 12 COMB LAB_X14_Y14 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.131 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[11\]~197'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[10]~195 Cout[11]~197 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.217 ns Cout\[12\]~199 13 COMB LAB_X14_Y14 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.217 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[12\]~199'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[11]~197 Cout[12]~199 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.303 ns Cout\[13\]~201 14 COMB LAB_X14_Y14 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.303 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[13\]~201'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[12]~199 Cout[13]~201 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.389 ns Cout\[14\]~203 15 COMB LAB_X14_Y14 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.389 ns; Loc. = LAB_X14_Y14; Fanout = 2; COMB Node = 'Cout\[14\]~203'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[13]~201 Cout[14]~203 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.107 ns) + CELL(0.086 ns) 2.582 ns Cout\[15\]~205 16 COMB LAB_X14_Y13 2 " "Info: 16: + IC(0.107 ns) + CELL(0.086 ns) = 2.582 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[15\]~205'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.193 ns" { Cout[14]~203 Cout[15]~205 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.668 ns Cout\[16\]~207 17 COMB LAB_X14_Y13 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.668 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[16\]~207'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[15]~205 Cout[16]~207 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.754 ns Cout\[17\]~209 18 COMB LAB_X14_Y13 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.754 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[17\]~209'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[16]~207 Cout[17]~209 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.840 ns Cout\[18\]~211 19 COMB LAB_X14_Y13 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.840 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[18\]~211'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[17]~209 Cout[18]~211 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.926 ns Cout\[19\]~213 20 COMB LAB_X14_Y13 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 2.926 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[19\]~213'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[18]~211 Cout[19]~213 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.012 ns Cout\[20\]~215 21 COMB LAB_X14_Y13 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.012 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[20\]~215'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[19]~213 Cout[20]~215 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.098 ns Cout\[21\]~217 22 COMB LAB_X14_Y13 2 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.098 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[21\]~217'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[20]~215 Cout[21]~217 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.184 ns Cout\[22\]~219 23 COMB LAB_X14_Y13 2 " "Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.184 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[22\]~219'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[21]~217 Cout[22]~219 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.270 ns Cout\[23\]~221 24 COMB LAB_X14_Y13 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.270 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[23\]~221'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[22]~219 Cout[23]~221 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.356 ns Cout\[24\]~223 25 COMB LAB_X14_Y13 2 " "Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.356 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[24\]~223'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[23]~221 Cout[24]~223 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.442 ns Cout\[25\]~225 26 COMB LAB_X14_Y13 2 " "Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.442 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[25\]~225'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[24]~223 Cout[25]~225 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.528 ns Cout\[26\]~227 27 COMB LAB_X14_Y13 2 " "Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.528 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[26\]~227'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[25]~225 Cout[26]~227 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.614 ns Cout\[27\]~229 28 COMB LAB_X14_Y13 2 " "Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.614 ns; Loc. = LAB_X14_Y13; Fanout = 2; COMB Node = 'Cout\[27\]~229'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[26]~227 Cout[27]~229 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.700 ns Cout\[28\]~231 29 COMB LAB_X14_Y13 1 " "Info: 29: + IC(0.000 ns) + CELL(0.086 ns) = 3.700 ns; Loc. = LAB_X14_Y13; Fanout = 1; COMB Node = 'Cout\[28\]~231'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[27]~229 Cout[28]~231 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.206 ns Cout\[29\]~232 30 COMB LAB_X14_Y13 1 " "Info: 30: + IC(0.000 ns) + CELL(0.506 ns) = 4.206 ns; Loc. = LAB_X14_Y13; Fanout = 1; COMB Node = 'Cout\[29\]~232'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Cout[28]~231 Cout[29]~232 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.314 ns Cout\[29\] 31 REG LAB_X14_Y13 2 " "Info: 31: + IC(0.000 ns) + CELL(0.108 ns) = 4.314 ns; Loc. = LAB_X14_Y13; Fanout = 2; REG Node = 'Cout\[29\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Cout[29]~232 Cout[29] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.532 ns ( 81.87 % ) " "Info: Total cell delay = 3.532 ns ( 81.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 18.13 % ) " "Info: Total interconnect delay = 0.782 ns ( 18.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.314 ns" { Cout[0] Cout[1]~177 Cout[2]~179 Cout[3]~181 Cout[4]~183 Cout[5]~185 Cout[6]~187 Cout[7]~189 Cout[8]~191 Cout[9]~193 Cout[10]~195 Cout[11]~197 Cout[12]~199 Cout[13]~201 Cout[14]~203 Cout[15]~205 Cout[16]~207 Cout[17]~209 Cout[18]~211 Cout[19]~213 Cout[20]~215 Cout[21]~217 Cout[22]~219 Cout[23]~221 Cout[24]~223 Cout[25]~225 Cout[26]~227 Cout[27]~229 Cout[28]~231 Cout[29]~232 Cout[29] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X10_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}