segment1.tan.rpt

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Jul 02 22:01:46 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Segment1 -c Segment1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clk" is an undefined clock
Info: Clock "Clk" has Internal fmax of 208.25 MHz between source register "Cout[1]" and destination register "Cout[28]" (period= 4.802 ns)
    Info: + Longest register to register delay is 4.522 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y14_N5; Fanout = 2; REG Node = 'Cout[1]'
        Info: 2: + IC(0.754 ns) + CELL(0.621 ns) = 1.375 ns; Loc. = LCCOMB_X14_Y14_N4; Fanout = 2; COMB Node = 'Cout[1]~176'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.461 ns; Loc. = LCCOMB_X14_Y14_N6; Fanout = 2; COMB Node = 'Cout[2]~178'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.547 ns; Loc. = LCCOMB_X14_Y14_N8; Fanout = 2; COMB Node = 'Cout[3]~180'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.633 ns; Loc. = LCCOMB_X14_Y14_N10; Fanout = 2; COMB Node = 'Cout[4]~182'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.719 ns; Loc. = LCCOMB_X14_Y14_N12; Fanout = 2; COMB Node = 'Cout[5]~184'
        Info: 7: + IC(0.000 ns) + CELL(0.190 ns) = 1.909 ns; Loc. = LCCOMB_X14_Y14_N14; Fanout = 2; COMB Node = 'Cout[6]~186'
        Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.995 ns; Loc. = LCCOMB_X14_Y14_N16; Fanout = 2; COMB Node = 'Cout[7]~188'
        Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.081 ns; Loc. = LCCOMB_X14_Y14_N18; Fanout = 2; COMB Node = 'Cout[8]~190'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.167 ns; Loc. = LCCOMB_X14_Y14_N20; Fanout = 2; COMB Node = 'Cout[9]~192'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.253 ns; Loc. = LCCOMB_X14_Y14_N22; Fanout = 2; COMB Node = 'Cout[10]~194'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.339 ns; Loc. = LCCOMB_X14_Y14_N24; Fanout = 2; COMB Node = 'Cout[11]~196'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.425 ns; Loc. = LCCOMB_X14_Y14_N26; Fanout = 2; COMB Node = 'Cout[12]~198'
        Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.511 ns; Loc. = LCCOMB_X14_Y14_N28; Fanout = 2; COMB Node = 'Cout[13]~200'
        Info: 15: + IC(0.000 ns) + CELL(0.175 ns) = 2.686 ns; Loc. = LCCOMB_X14_Y14_N30; Fanout = 2; COMB Node = 'Cout[14]~202'
        Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.772 ns; Loc. = LCCOMB_X14_Y13_N0; Fanout = 2; COMB Node = 'Cout[15]~204'
        Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.858 ns; Loc. = LCCOMB_X14_Y13_N2; Fanout = 2; COMB Node = 'Cout[16]~206'
        Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.944 ns; Loc. = LCCOMB_X14_Y13_N4; Fanout = 2; COMB Node = 'Cout[17]~208'
        Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.030 ns; Loc. = LCCOMB_X14_Y13_N6; Fanout = 2; COMB Node = 'Cout[18]~210'
        Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.116 ns; Loc. = LCCOMB_X14_Y13_N8; Fanout = 2; COMB Node = 'Cout[19]~212'
        Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.202 ns; Loc. = LCCOMB_X14_Y13_N10; Fanout = 2; COMB Node = 'Cout[20]~214'
        Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.288 ns; Loc. = LCCOMB_X14_Y13_N12; Fanout = 2; COMB Node = 'Cout[21]~216'
        Info: 23: + IC(0.000 ns) + CELL(0.190 ns) = 3.478 ns; Loc. = LCCOMB_X14_Y13_N14; Fanout = 2; COMB Node = 'Cout[22]~218'
        Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.564 ns; Loc. = LCCOMB_X14_Y13_N16; Fanout = 2; COMB Node = 'Cout[23]~220'
        Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.650 ns; Loc. = LCCOMB_X14_Y13_N18; Fanout = 2; COMB Node = 'Cout[24]~222'
        Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.736 ns; Loc. = LCCOMB_X14_Y13_N20; Fanout = 2; COMB Node = 'Cout[25]~224'
        Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.822 ns; Loc. = LCCOMB_X14_Y13_N22; Fanout = 2; COMB Node = 'Cout[26]~226'
        Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.908 ns; Loc. = LCCOMB_X14_Y13_N24; Fanout = 1; COMB Node = 'Cout[27]~228'
        Info: 29: + IC(0.000 ns) + CELL(0.506 ns) = 4.414 ns; Loc. = LCCOMB_X14_Y13_N26; Fanout = 1; COMB Node = 'Cout[28]~229'
        Info: 30: + IC(0.000 ns) + CELL(0.108 ns) = 4.522 ns; Loc. = LCFF_X14_Y13_N27; Fanout = 2; REG Node = 'Cout[28]'
        Info: Total cell delay = 3.768 ns ( 83.33 % )
        Info: Total interconnect delay = 0.754 ns ( 16.67 % )
    Info: - Smallest clock skew is -0.016 ns
        Info: + Shortest clock path from clock "Clk" to destination register is 2.855 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'Clk~clkctrl'
            Info: 3: + IC(0.910 ns) + CELL(0.666 ns) = 2.855 ns; Loc. = LCFF_X14_Y13_N27; Fanout = 2; REG Node = 'Cout[28]'
            Info: Total cell delay = 1.806 ns ( 63.26 % )
            Info: Total interconnect delay = 1.049 ns ( 36.74 % )
        Info: - Longest clock path from clock "Clk" to source register is 2.871 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'Clk~clkctrl'
            Info: 3: + IC(0.926 ns) + CELL(0.666 ns) = 2.871 ns; Loc. = LCFF_X14_Y14_N5; Fanout = 2; REG Node = 'Cout[1]'
            Info: Total cell delay = 1.806 ns ( 62.90 % )
            Info: Total interconnect delay = 1.065 ns ( 37.10 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "Clk" to destination pin "Sev_Seg_Led_Data_n[4]" through register "Sev_Seg_Led_Data_n[4]~reg0" is 8.544 ns
    Info: + Longest clock path from clock "Clk" to source register is 2.850 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'Clk~clkctrl'
        Info: 3: + IC(0.905 ns) + CELL(0.666 ns) = 2.850 ns; Loc. = LCFF_X10_Y13_N1; Fanout = 1; REG Node = 'Sev_Seg_Led_Data_n[4]~reg0'
        Info: Total cell delay = 1.806 ns ( 63.37 % )
        Info: Total interconnect delay = 1.044 ns ( 36.63 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.390 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y13_N1; Fanout = 1; REG Node = 'Sev_Seg_Led_Data_n[4]~reg0'
        Info: 2: + IC(2.104 ns) + CELL(3.286 ns) = 5.390 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Sev_Seg_Led_Data_n[4]'
        Info: Total cell delay = 3.286 ns ( 60.96 % )
        Info: Total interconnect delay = 2.104 ns ( 39.04 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Wed Jul 02 22:01:47 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01