segment1.map.rpt

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                 ;
+----------------------------------+-----------------+-----------+-------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path                          ;
+----------------------------------+-----------------+-----------+-------------------------------------------------------+
; Segment1.v                       ; yes             ; Other     ; F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v ;
+----------------------------------+-----------------+-----------+-------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 40    ;
;                                             ;       ;
; Total combinational functions               ; 36    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 7     ;
;     -- 3 input functions                    ; 1     ;
;     -- <=2 input functions                  ; 28    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 9     ;
;     -- arithmetic mode                      ; 27    ;
;                                             ;       ;
; Total registers                             ; 40    ;
;     -- Dedicated logic registers            ; 40    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 15    ;
; Maximum fan-out node                        ; Clk   ;
; Maximum fan-out                             ; 40    ;
; Total fan-out                               ; 172   ;
; Average fan-out                             ; 1.89  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |Segment1                  ; 36 (36)           ; 40 (40)      ; 0           ; 0            ; 0       ; 0         ; 15   ; 0            ; |Segment1           ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; Sev_Seg_Led_Data_n[7]~reg0            ; Stuck at GND due to stuck port data_in ;
; Cout[29]                              ; Lost fanout                            ;
; Total Number of Removed Registers = 2 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 40    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Jul 02 22:01:33 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Segment1 -c Segment1
Warning: Using design file Segment1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: Segment1
Info: Elaborating entity "Segment1" for the top level hierarchy
Warning (14130): Reduced register "Sev_Seg_Led_Data_n[7]~reg0" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "Sev_Seg_Led_Sel_n[0]" is stuck at GND
    Warning (13410): Pin "Sev_Seg_Led_Sel_n[1]" is stuck at GND
    Warning (13410): Pin "Sev_Seg_Led_Sel_n[2]" is stuck at GND
    Warning (13410): Pin "Sev_Seg_Led_Sel_n[3]" is stuck at GND
    Warning (13410): Pin "Sev_Seg_Led_Data_n[7]" is stuck at GND
    Warning (13410): Pin "Led_En_n" is stuck at VCC
    Warning (13410): Pin "Buzz" is stuck at GND
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "Cout[29]" lost all its fanouts during netlist optimizations.
Info: Implemented 55 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 14 output pins
    Info: Implemented 40 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Peak virtual memory: 156 megabytes
    Info: Processing ended: Wed Jul 02 22:01:35 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02