flicker_led.fit.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "14 " "Warning: Found 14 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led_En_n 0 " "Info: Pin \"Led_En_n\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[0\] 0 " "Info: Pin \"Led\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[1\] 0 " "Info: Pin \"Led\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[2\] 0 " "Info: Pin \"Led\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[3\] 0 " "Info: Pin \"Led\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[4\] 0 " "Info: Pin \"Led\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[5\] 0 " "Info: Pin \"Led\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[6\] 0 " "Info: Pin \"Led\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Led\[7\] 0 " "Info: Pin \"Led\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Buzz 0 " "Info: Pin \"Buzz\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Sel_n\[0\] 0 " "Info: Pin \"Sev_Seg_Led_Sel_n\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Sel_n\[1\] 0 " "Info: Pin \"Sev_Seg_Led_Sel_n\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Sel_n\[2\] 0 " "Info: Pin \"Sev_Seg_Led_Sel_n\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Sev_Seg_Led_Sel_n\[3\] 0 " "Info: Pin \"Sev_Seg_Led_Sel_n\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "6 " "Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Led_En_n GND " "Info: Pin Led_En_n has GND driving its datain port" {  } { { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { Led_En_n } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Led_En_n" } } } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 15 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Led_En_n } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Buzz GND " "Info: Pin Buzz has GND driving its datain port" {  } { { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { Buzz } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Buzz" } } } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 18 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Buzz } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Sev_Seg_Led_Sel_n\[0\] VCC " "Info: Pin Sev_Seg_Led_Sel_n\[0\] has VCC driving its datain port" {  } { { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { Sev_Seg_Led_Sel_n[0] } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Sel_n\[0\]" } } } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 19 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sev_Seg_Led_Sel_n[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Sev_Seg_Led_Sel_n\[1\] VCC " "Info: Pin Sev_Seg_Led_Sel_n\[1\] has VCC driving its datain port" {  } { { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { Sev_Seg_Led_Sel_n[1] } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Sel_n\[1\]" } } } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 19 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sev_Seg_Led_Sel_n[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Sev_Seg_Led_Sel_n\[2\] VCC " "Info: Pin Sev_Seg_Led_Sel_n\[2\] has VCC driving its datain port" {  } { { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { Sev_Seg_Led_Sel_n[2] } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Sel_n\[2\]" } } } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 19 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sev_Seg_Led_Sel_n[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Sev_Seg_Led_Sel_n\[3\] VCC " "Info: Pin Sev_Seg_Led_Sel_n\[3\] has VCC driving its datain port" {  } { { "d:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/80/quartus/bin/pin_planner.ppl" { Sev_Seg_Led_Sel_n[3] } } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Sev_Seg_Led_Sel_n\[3\]" } } } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 19 -1 0 } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sev_Seg_Led_Sel_n[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.fit.smsg " "Info: Generated suppressed messages file F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 41 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "186 " "Info: Peak virtual memory: 186 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 18:23:45 2008 " "Info: Processing ended: Wed Jul 02 18:23:45 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}