prev_cmp_flicker_led.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 26 19:27:31 2008 " "Info: Processing started: Thu Jun 26 19:27:31 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Flicker_Led -c Flicker_Led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Flicker_Led -c Flicker_Led" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"always\";  expecting \"@\", or \"end\", or an identifier (\"always\" is a reserved keyword ), or a system task, or \"\{\", or a sequential statement Flicker_Led.v(41) " "Error (10170): Verilog HDL syntax error at Flicker_Led.v(41) near text \"always\";  expecting \"@\", or \"end\", or an identifier (\"always\" is a reserved keyword ), or a system task, or \"\{\", or a sequential statement" {  } { { "Flicker_Led.v" "" { Text "I:/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 41 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"always\";  expecting \"@\", or \"end\", or an identifier (\"always\" is a reserved keyword ), or a system task, or \"\{\", or a sequential statement Flicker_Led.v(58) " "Error (10170): Verilog HDL syntax error at Flicker_Led.v(58) near text \"always\";  expecting \"@\", or \"end\", or an identifier (\"always\" is a reserved keyword ), or a system task, or \"\{\", or a sequential statement" {  } { { "Flicker_Led.v" "" { Text "I:/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 58 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"endmodule\";  expecting \"@\", or \"end\", or an identifier (\"endmodule\" is a reserved keyword ), or a system task, or \"\{\", or a sequential statement Flicker_Led.v(82) " "Error (10170): Verilog HDL syntax error at Flicker_Led.v(82) near text \"endmodule\";  expecting \"@\", or \"end\", or an identifier (\"endmodule\" is a reserved keyword ), or a system task, or \"\{\", or a sequential statement" {  } { { "Flicker_Led.v" "" { Text "I:/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 82 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Flicker_Led.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file Flicker_Led.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jun 26 19:27:38 2008 " "Error: Processing ended: Thu Jun 26 19:27:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Error: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}