📄 flicker_led.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" { } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 12 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register Cout\[0\] register Cout\[24\] 174.86 MHz 5.719 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 174.86 MHz between source register \"Cout\[0\]\" and destination register \"Cout\[24\]\" (period= 5.719 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.474 ns + Longest register register " "Info: + Longest register to register delay is 5.474 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[0\] 1 REG LCFF_X29_Y7_N15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y7_N15; Fanout = 3; REG Node = 'Cout\[0\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[0] } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.678 ns) + CELL(0.621 ns) 1.299 ns Add0~385 2 COMB LCCOMB_X30_Y7_N0 2 " "Info: 2: + IC(0.678 ns) + CELL(0.621 ns) = 1.299 ns; Loc. = LCCOMB_X30_Y7_N0; Fanout = 2; COMB Node = 'Add0~385'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { Cout[0] Add0~385 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.385 ns Add0~387 3 COMB LCCOMB_X30_Y7_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.385 ns; Loc. = LCCOMB_X30_Y7_N2; Fanout = 2; COMB Node = 'Add0~387'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~385 Add0~387 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.471 ns Add0~389 4 COMB LCCOMB_X30_Y7_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.471 ns; Loc. = LCCOMB_X30_Y7_N4; Fanout = 2; COMB Node = 'Add0~389'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~387 Add0~389 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.557 ns Add0~391 5 COMB LCCOMB_X30_Y7_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.557 ns; Loc. = LCCOMB_X30_Y7_N6; Fanout = 2; COMB Node = 'Add0~391'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~389 Add0~391 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.643 ns Add0~393 6 COMB LCCOMB_X30_Y7_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.643 ns; Loc. = LCCOMB_X30_Y7_N8; Fanout = 2; COMB Node = 'Add0~393'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~391 Add0~393 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.729 ns Add0~395 7 COMB LCCOMB_X30_Y7_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.729 ns; Loc. = LCCOMB_X30_Y7_N10; Fanout = 2; COMB Node = 'Add0~395'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~393 Add0~395 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.815 ns Add0~397 8 COMB LCCOMB_X30_Y7_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.815 ns; Loc. = LCCOMB_X30_Y7_N12; Fanout = 2; COMB Node = 'Add0~397'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~395 Add0~397 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 2.005 ns Add0~399 9 COMB LCCOMB_X30_Y7_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.190 ns) = 2.005 ns; Loc. = LCCOMB_X30_Y7_N14; Fanout = 2; COMB Node = 'Add0~399'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Add0~397 Add0~399 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.091 ns Add0~401 10 COMB LCCOMB_X30_Y7_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.091 ns; Loc. = LCCOMB_X30_Y7_N16; Fanout = 2; COMB Node = 'Add0~401'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~399 Add0~401 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.177 ns Add0~403 11 COMB LCCOMB_X30_Y7_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.177 ns; Loc. = LCCOMB_X30_Y7_N18; Fanout = 2; COMB Node = 'Add0~403'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~401 Add0~403 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.263 ns Add0~405 12 COMB LCCOMB_X30_Y7_N20 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.263 ns; Loc. = LCCOMB_X30_Y7_N20; Fanout = 2; COMB Node = 'Add0~405'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~403 Add0~405 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.349 ns Add0~407 13 COMB LCCOMB_X30_Y7_N22 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.349 ns; Loc. = LCCOMB_X30_Y7_N22; Fanout = 2; COMB Node = 'Add0~407'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~405 Add0~407 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.435 ns Add0~409 14 COMB LCCOMB_X30_Y7_N24 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.435 ns; Loc. = LCCOMB_X30_Y7_N24; Fanout = 2; COMB Node = 'Add0~409'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~407 Add0~409 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.521 ns Add0~411 15 COMB LCCOMB_X30_Y7_N26 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.521 ns; Loc. = LCCOMB_X30_Y7_N26; Fanout = 2; COMB Node = 'Add0~411'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~409 Add0~411 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.607 ns Add0~413 16 COMB LCCOMB_X30_Y7_N28 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.607 ns; Loc. = LCCOMB_X30_Y7_N28; Fanout = 2; COMB Node = 'Add0~413'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~411 Add0~413 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 2.782 ns Add0~415 17 COMB LCCOMB_X30_Y7_N30 2 " "Info: 17: + IC(0.000 ns) + CELL(0.175 ns) = 2.782 ns; Loc. = LCCOMB_X30_Y7_N30; Fanout = 2; COMB Node = 'Add0~415'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.175 ns" { Add0~413 Add0~415 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.868 ns Add0~417 18 COMB LCCOMB_X30_Y6_N0 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.868 ns; Loc. = LCCOMB_X30_Y6_N0; Fanout = 2; COMB Node = 'Add0~417'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~415 Add0~417 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.954 ns Add0~419 19 COMB LCCOMB_X30_Y6_N2 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.954 ns; Loc. = LCCOMB_X30_Y6_N2; Fanout = 2; COMB Node = 'Add0~419'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~417 Add0~419 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.040 ns Add0~421 20 COMB LCCOMB_X30_Y6_N4 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.040 ns; Loc. = LCCOMB_X30_Y6_N4; Fanout = 2; COMB Node = 'Add0~421'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~419 Add0~421 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.126 ns Add0~423 21 COMB LCCOMB_X30_Y6_N6 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.126 ns; Loc. = LCCOMB_X30_Y6_N6; Fanout = 2; COMB Node = 'Add0~423'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~421 Add0~423 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.212 ns Add0~425 22 COMB LCCOMB_X30_Y6_N8 2 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.212 ns; Loc. = LCCOMB_X30_Y6_N8; Fanout = 2; COMB Node = 'Add0~425'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~423 Add0~425 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.298 ns Add0~427 23 COMB LCCOMB_X30_Y6_N10 2 " "Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.298 ns; Loc. = LCCOMB_X30_Y6_N10; Fanout = 2; COMB Node = 'Add0~427'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~425 Add0~427 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.384 ns Add0~429 24 COMB LCCOMB_X30_Y6_N12 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.384 ns; Loc. = LCCOMB_X30_Y6_N12; Fanout = 2; COMB Node = 'Add0~429'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~427 Add0~429 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 3.574 ns Add0~431 25 COMB LCCOMB_X30_Y6_N14 2 " "Info: 25: + IC(0.000 ns) + CELL(0.190 ns) = 3.574 ns; Loc. = LCCOMB_X30_Y6_N14; Fanout = 2; COMB Node = 'Add0~431'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Add0~429 Add0~431 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.080 ns Add0~432 26 COMB LCCOMB_X30_Y6_N16 1 " "Info: 26: + IC(0.000 ns) + CELL(0.506 ns) = 4.080 ns; Loc. = LCCOMB_X30_Y6_N16; Fanout = 1; COMB Node = 'Add0~432'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~431 Add0~432 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.080 ns) + CELL(0.206 ns) 5.366 ns Cout~266 27 COMB LCCOMB_X30_Y4_N12 1 " "Info: 27: + IC(1.080 ns) + CELL(0.206 ns) = 5.366 ns; Loc. = LCCOMB_X30_Y4_N12; Fanout = 1; COMB Node = 'Cout~266'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { Add0~432 Cout~266 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.474 ns Cout\[24\] 28 REG LCFF_X30_Y4_N13 3 " "Info: 28: + IC(0.000 ns) + CELL(0.108 ns) = 5.474 ns; Loc. = LCFF_X30_Y4_N13; Fanout = 3; REG Node = 'Cout\[24\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Cout~266 Cout[24] } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.716 ns ( 67.88 % ) " "Info: Total cell delay = 3.716 ns ( 67.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.758 ns ( 32.12 % ) " "Info: Total interconnect delay = 1.758 ns ( 32.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.474 ns" { Cout[0] Add0~385 Add0~387 Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~432 Cout~266 Cout[24] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.474 ns" { Cout[0] {} Add0~385 {} Add0~387 {} Add0~389 {} Add0~391 {} Add0~393 {} Add0~395 {} Add0~397 {} Add0~399 {} Add0~401 {} Add0~403 {} Add0~405 {} Add0~407 {} Add0~409 {} Add0~411 {} Add0~413 {} Add0~415 {} Add0~417 {} Add0~419 {} Add0~421 {} Add0~423 {} Add0~425 {} Add0~427 {} Add0~429 {} Add0~431 {} Add0~432 {} Cout~266 {} Cout[24] {} } { 0.000ns 0.678ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.080ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.506ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.019 ns - Smallest " "Info: - Smallest clock skew is 0.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.872 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.666 ns) 2.872 ns Cout\[24\] 3 REG LCFF_X30_Y4_N13 3 " "Info: 3: + IC(0.927 ns) + CELL(0.666 ns) = 2.872 ns; Loc. = LCFF_X30_Y4_N13; Fanout = 3; REG Node = 'Cout\[24\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.593 ns" { Clk~clkctrl Cout[24] } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.88 % ) " "Info: Total cell delay = 1.806 ns ( 62.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 37.12 % ) " "Info: Total interconnect delay = 1.066 ns ( 37.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Clk Clk~clkctrl Cout[24] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[24] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.853 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(0.666 ns) 2.853 ns Cout\[0\] 3 REG LCFF_X29_Y7_N15 3 " "Info: 3: + IC(0.908 ns) + CELL(0.666 ns) = 2.853 ns; Loc. = LCFF_X29_Y7_N15; Fanout = 3; REG Node = 'Cout\[0\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { Clk~clkctrl Cout[0] } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.30 % ) " "Info: Total cell delay = 1.806 ns ( 63.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.047 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.047 ns ( 36.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { Clk Clk~clkctrl Cout[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[0] {} } { 0.000ns 0.000ns 0.139ns 0.908ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Clk Clk~clkctrl Cout[24] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[24] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { Clk Clk~clkctrl Cout[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[0] {} } { 0.000ns 0.000ns 0.139ns 0.908ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 34 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 34 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.474 ns" { Cout[0] Add0~385 Add0~387 Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~432 Cout~266 Cout[24] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.474 ns" { Cout[0] {} Add0~385 {} Add0~387 {} Add0~389 {} Add0~391 {} Add0~393 {} Add0~395 {} Add0~397 {} Add0~399 {} Add0~401 {} Add0~403 {} Add0~405 {} Add0~407 {} Add0~409 {} Add0~411 {} Add0~413 {} Add0~415 {} Add0~417 {} Add0~419 {} Add0~421 {} Add0~423 {} Add0~425 {} Add0~427 {} Add0~429 {} Add0~431 {} Add0~432 {} Cout~266 {} Cout[24] {} } { 0.000ns 0.678ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.080ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.506ns 0.206ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Clk Clk~clkctrl Cout[24] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[24] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { Clk Clk~clkctrl Cout[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[0] {} } { 0.000ns 0.000ns 0.139ns 0.908ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Led\[5\] Led\[0\]~reg0 10.980 ns register " "Info: tco from clock \"Clk\" to destination pin \"Led\[5\]\" through register \"Led\[0\]~reg0\" is 10.980 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.853 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 34 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(0.666 ns) 2.853 ns Led\[0\]~reg0 3 REG LCFF_X29_Y7_N9 9 " "Info: 3: + IC(0.908 ns) + CELL(0.666 ns) = 2.853 ns; Loc. = LCFF_X29_Y7_N9; Fanout = 9; REG Node = 'Led\[0\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { Clk~clkctrl Led[0]~reg0 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.30 % ) " "Info: Total cell delay = 1.806 ns ( 63.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.047 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.047 ns ( 36.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { Clk Clk~clkctrl Led[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Led[0]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.908ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.823 ns + Longest register pin " "Info: + Longest register to pin delay is 7.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Led\[0\]~reg0 1 REG LCFF_X29_Y7_N9 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y7_N9; Fanout = 9; REG Node = 'Led\[0\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Led[0]~reg0 } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.517 ns) + CELL(3.306 ns) 7.823 ns Led\[5\] 2 PIN PIN_207 0 " "Info: 2: + IC(4.517 ns) + CELL(3.306 ns) = 7.823 ns; Loc. = PIN_207; Fanout = 0; PIN Node = 'Led\[5\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.823 ns" { Led[0]~reg0 Led[5] } "NODE_NAME" } } { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.306 ns ( 42.26 % ) " "Info: Total cell delay = 3.306 ns ( 42.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.517 ns ( 57.74 % ) " "Info: Total interconnect delay = 4.517 ns ( 57.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.823 ns" { Led[0]~reg0 Led[5] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.823 ns" { Led[0]~reg0 {} Led[5] {} } { 0.000ns 4.517ns } { 0.000ns 3.306ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { Clk Clk~clkctrl Led[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Led[0]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.908ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.823 ns" { Led[0]~reg0 Led[5] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.823 ns" { Led[0]~reg0 {} Led[5] {} } { 0.000ns 4.517ns } { 0.000ns 3.306ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
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