flicker_led.map.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 18:23:25 2008 " "Info: Processing started: Wed Jul 02 18:23:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Flicker_Led -c Flicker_Led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Flicker_Led -c Flicker_Led" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Flicker_Led.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Flicker_Led.v" { { "Info" "ISGN_ENTITY_NAME" "1 Flicker_Led " "Info: Found entity 1: Flicker_Led" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Flicker_Led " "Info: Elaborating entity \"Flicker_Led\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Led\[1\]~reg0 Led\[0\]~reg0 " "Info (13350): Duplicate register \"Led\[1\]~reg0\" merged to single register \"Led\[0\]~reg0\"" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Led\[4\]~reg0 Led\[0\]~reg0 " "Info (13350): Duplicate register \"Led\[4\]~reg0\" merged to single register \"Led\[0\]~reg0\"" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Led\[7\]~reg0 Led\[0\]~reg0 " "Info (13350): Duplicate register \"Led\[7\]~reg0\" merged to single register \"Led\[0\]~reg0\"" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Led\[5\]~reg0 Led\[0\]~reg0 " "Info (13350): Duplicate register \"Led\[5\]~reg0\" merged to single register \"Led\[0\]~reg0\"" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Led\[3\]~reg0 Led\[0\]~reg0 " "Info (13350): Duplicate register \"Led\[3\]~reg0\" merged to single register \"Led\[0\]~reg0\"" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Led\[6\]~reg0 Led\[0\]~reg0 " "Info (13350): Duplicate register \"Led\[6\]~reg0\" merged to single register \"Led\[0\]~reg0\"" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "Led\[2\]~reg0 Led\[0\]~reg0 " "Info (13350): Duplicate register \"Led\[2\]~reg0\" merged to single register \"Led\[0\]~reg0\"" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 65 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "Led_En_n GND " "Warning (13410): Pin \"Led_En_n\" is stuck at GND" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 15 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Buzz GND " "Warning (13410): Pin \"Buzz\" is stuck at GND" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 18 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Sel_n\[0\] VCC " "Warning (13410): Pin \"Sev_Seg_Led_Sel_n\[0\]\" is stuck at VCC" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Sel_n\[1\] VCC " "Warning (13410): Pin \"Sev_Seg_Led_Sel_n\[1\]\" is stuck at VCC" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Sel_n\[2\] VCC " "Warning (13410): Pin \"Sev_Seg_Led_Sel_n\[2\]\" is stuck at VCC" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Sel_n\[3\] VCC " "Warning (13410): Pin \"Sev_Seg_Led_Sel_n\[3\]\" is stuck at VCC" {  } { { "Flicker_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flicker_Led/Flicker_Led/Flicker_Led.v" 19 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "74 " "Info: Implemented 74 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "58 " "Info: Implemented 58 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Peak virtual memory: 156 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 18:23:31 2008 " "Info: Processing ended: Wed Jul 02 18:23:31 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}