flicker_led.tan.rpt

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Jul 02 18:23:57 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Flicker_Led -c Flicker_Led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clk" is an undefined clock
Info: Clock "Clk" has Internal fmax of 174.86 MHz between source register "Cout[0]" and destination register "Cout[24]" (period= 5.719 ns)
    Info: + Longest register to register delay is 5.474 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y7_N15; Fanout = 3; REG Node = 'Cout[0]'
        Info: 2: + IC(0.678 ns) + CELL(0.621 ns) = 1.299 ns; Loc. = LCCOMB_X30_Y7_N0; Fanout = 2; COMB Node = 'Add0~385'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.385 ns; Loc. = LCCOMB_X30_Y7_N2; Fanout = 2; COMB Node = 'Add0~387'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.471 ns; Loc. = LCCOMB_X30_Y7_N4; Fanout = 2; COMB Node = 'Add0~389'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.557 ns; Loc. = LCCOMB_X30_Y7_N6; Fanout = 2; COMB Node = 'Add0~391'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.643 ns; Loc. = LCCOMB_X30_Y7_N8; Fanout = 2; COMB Node = 'Add0~393'
        Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.729 ns; Loc. = LCCOMB_X30_Y7_N10; Fanout = 2; COMB Node = 'Add0~395'
        Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.815 ns; Loc. = LCCOMB_X30_Y7_N12; Fanout = 2; COMB Node = 'Add0~397'
        Info: 9: + IC(0.000 ns) + CELL(0.190 ns) = 2.005 ns; Loc. = LCCOMB_X30_Y7_N14; Fanout = 2; COMB Node = 'Add0~399'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.091 ns; Loc. = LCCOMB_X30_Y7_N16; Fanout = 2; COMB Node = 'Add0~401'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.177 ns; Loc. = LCCOMB_X30_Y7_N18; Fanout = 2; COMB Node = 'Add0~403'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.263 ns; Loc. = LCCOMB_X30_Y7_N20; Fanout = 2; COMB Node = 'Add0~405'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.349 ns; Loc. = LCCOMB_X30_Y7_N22; Fanout = 2; COMB Node = 'Add0~407'
        Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.435 ns; Loc. = LCCOMB_X30_Y7_N24; Fanout = 2; COMB Node = 'Add0~409'
        Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.521 ns; Loc. = LCCOMB_X30_Y7_N26; Fanout = 2; COMB Node = 'Add0~411'
        Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.607 ns; Loc. = LCCOMB_X30_Y7_N28; Fanout = 2; COMB Node = 'Add0~413'
        Info: 17: + IC(0.000 ns) + CELL(0.175 ns) = 2.782 ns; Loc. = LCCOMB_X30_Y7_N30; Fanout = 2; COMB Node = 'Add0~415'
        Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.868 ns; Loc. = LCCOMB_X30_Y6_N0; Fanout = 2; COMB Node = 'Add0~417'
        Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.954 ns; Loc. = LCCOMB_X30_Y6_N2; Fanout = 2; COMB Node = 'Add0~419'
        Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.040 ns; Loc. = LCCOMB_X30_Y6_N4; Fanout = 2; COMB Node = 'Add0~421'
        Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.126 ns; Loc. = LCCOMB_X30_Y6_N6; Fanout = 2; COMB Node = 'Add0~423'
        Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.212 ns; Loc. = LCCOMB_X30_Y6_N8; Fanout = 2; COMB Node = 'Add0~425'
        Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.298 ns; Loc. = LCCOMB_X30_Y6_N10; Fanout = 2; COMB Node = 'Add0~427'
        Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.384 ns; Loc. = LCCOMB_X30_Y6_N12; Fanout = 2; COMB Node = 'Add0~429'
        Info: 25: + IC(0.000 ns) + CELL(0.190 ns) = 3.574 ns; Loc. = LCCOMB_X30_Y6_N14; Fanout = 2; COMB Node = 'Add0~431'
        Info: 26: + IC(0.000 ns) + CELL(0.506 ns) = 4.080 ns; Loc. = LCCOMB_X30_Y6_N16; Fanout = 1; COMB Node = 'Add0~432'
        Info: 27: + IC(1.080 ns) + CELL(0.206 ns) = 5.366 ns; Loc. = LCCOMB_X30_Y4_N12; Fanout = 1; COMB Node = 'Cout~266'
        Info: 28: + IC(0.000 ns) + CELL(0.108 ns) = 5.474 ns; Loc. = LCFF_X30_Y4_N13; Fanout = 3; REG Node = 'Cout[24]'
        Info: Total cell delay = 3.716 ns ( 67.88 % )
        Info: Total interconnect delay = 1.758 ns ( 32.12 % )
    Info: - Smallest clock skew is 0.019 ns
        Info: + Shortest clock path from clock "Clk" to destination register is 2.872 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'Clk~clkctrl'
            Info: 3: + IC(0.927 ns) + CELL(0.666 ns) = 2.872 ns; Loc. = LCFF_X30_Y4_N13; Fanout = 3; REG Node = 'Cout[24]'
            Info: Total cell delay = 1.806 ns ( 62.88 % )
            Info: Total interconnect delay = 1.066 ns ( 37.12 % )
        Info: - Longest clock path from clock "Clk" to source register is 2.853 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'Clk~clkctrl'
            Info: 3: + IC(0.908 ns) + CELL(0.666 ns) = 2.853 ns; Loc. = LCFF_X29_Y7_N15; Fanout = 3; REG Node = 'Cout[0]'
            Info: Total cell delay = 1.806 ns ( 63.30 % )
            Info: Total interconnect delay = 1.047 ns ( 36.70 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "Clk" to destination pin "Led[5]" through register "Led[0]~reg0" is 10.980 ns
    Info: + Longest clock path from clock "Clk" to source register is 2.853 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'Clk~clkctrl'
        Info: 3: + IC(0.908 ns) + CELL(0.666 ns) = 2.853 ns; Loc. = LCFF_X29_Y7_N9; Fanout = 9; REG Node = 'Led[0]~reg0'
        Info: Total cell delay = 1.806 ns ( 63.30 % )
        Info: Total interconnect delay = 1.047 ns ( 36.70 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 7.823 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y7_N9; Fanout = 9; REG Node = 'Led[0]~reg0'
        Info: 2: + IC(4.517 ns) + CELL(3.306 ns) = 7.823 ns; Loc. = PIN_207; Fanout = 0; PIN Node = 'Led[5]'
        Info: Total cell delay = 3.306 ns ( 42.26 % )
        Info: Total interconnect delay = 4.517 ns ( 57.74 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Wed Jul 02 18:23:58 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01