prev_cmp_basegate.map.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 15 09:28:24 2008 " "Info: Processing started: Tue Apr 15 09:28:24 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off BaseGate -c BaseGate " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off BaseGate -c BaseGate" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BaseGate.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file BaseGate.v" { { "Info" "ISGN_ENTITY_NAME" "1 BaseGate " "Info: Found entity 1: BaseGate" {  } { { "BaseGate.v" "" { Text "L:/FPGA4U/Example/FPGA4U/BaseGate/BaseGate/BaseGate.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "BaseGate " "Info: Elaborating entity \"BaseGate\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "Led_En_n GND " "Warning (13410): Pin \"Led_En_n\" stuck at GND" {  } { { "BaseGate.v" "" { Text "L:/FPGA4U/Example/FPGA4U/BaseGate/BaseGate/BaseGate.v" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Led\[3\] GND " "Warning (13410): Pin \"Led\[3\]\" stuck at GND" {  } { { "BaseGate.v" "" { Text "L:/FPGA4U/Example/FPGA4U/BaseGate/BaseGate/BaseGate.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Led\[4\] GND " "Warning (13410): Pin \"Led\[4\]\" stuck at GND" {  } { { "BaseGate.v" "" { Text "L:/FPGA4U/Example/FPGA4U/BaseGate/BaseGate/BaseGate.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Led\[5\] GND " "Warning (13410): Pin \"Led\[5\]\" stuck at GND" {  } { { "BaseGate.v" "" { Text "L:/FPGA4U/Example/FPGA4U/BaseGate/BaseGate/BaseGate.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Led\[6\] GND " "Warning (13410): Pin \"Led\[6\]\" stuck at GND" {  } { { "BaseGate.v" "" { Text "L:/FPGA4U/Example/FPGA4U/BaseGate/BaseGate/BaseGate.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Led\[7\] GND " "Warning (13410): Pin \"Led\[7\]\" stuck at GND" {  } { { "BaseGate.v" "" { Text "L:/FPGA4U/Example/FPGA4U/BaseGate/BaseGate/BaseGate.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Warning: Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Sw_n\[2\] " "Warning (15610): No output dependent on input pin \"Sw_n\[2\]\"" {  } { { "BaseGate.v" "" { Text "L:/FPGA4U/Example/FPGA4U/BaseGate/BaseGate/BaseGate.v" 7 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Sw_n\[3\] " "Warning (15610): No output dependent on input pin \"Sw_n\[3\]\"" {  } { { "BaseGate.v" "" { Text "L:/FPGA4U/Example/FPGA4U/BaseGate/BaseGate/BaseGate.v" 7 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "14 " "Info: Implemented 14 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Info: Implemented 1 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 15 09:28:29 2008 " "Info: Processing ended: Tue Apr 15 09:28:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}