flow_led.v

来自「采用Altera公司的CycloneII芯片EP2C8的一些程序代码。」· Verilog 代码 · 共 66 行

module Flow_Led (
					Rst_n,					
					Clk,
										
					Led_En_n,
					Led,
					Buzz,
					Sev_Seg_Led_Sel_n
				);
input Rst_n;				
input Clk;

output Led_En_n;
output [7:0] Led;

output Buzz;
output [3:0] Sev_Seg_Led_Sel_n;
	
reg[7:0] Led;
reg [31:0] Cout;
reg Clk_En;
reg [2:0] i; 

	assign 
		Led_En_n = 1'd0;  //led使能，低有效	
		
	always @(posedge Clk or negedge Rst_n)
		begin
			if(~Rst_n)
				begin
					Cout <= 32'd0;
					Clk_En <= 1'd0;
					i <= 3'd0;
					Led <= 8'd0;
				end
			else
				begin
					Cout <= (Cout == 32'd12_000_000) ? 32'd0 : (Cout + 32'd1);
					Clk_En <= (Cout == 32'd12_000_000) ? 1'd1 : 1'd0;
					
					if(Clk_En)  //==0.5s
						begin
							i <= i + 3'd1;
						end
					
					case (i)
						3'd0: Led <= 8'b0000_0001;
						3'd1: Led <= 8'b0000_0010;
						3'd2: Led <= 8'b0000_0100;
						3'd3: Led <= 8'b0000_1000;
						3'd4: Led <= 8'b0001_0000;
						3'd5: Led <= 8'b0010_0000;
						3'd6: Led <= 8'b0100_0000;
						3'd7: Led <= 8'b1000_0000;
						default : Led <= 8'b0000_0001;
					endcase
				end
		end

	assign
		Buzz = 1'd0;  //禁止蜂鸣器工作
		
	assign
		Sev_Seg_Led_Sel_n = 4'b1111;  //禁止七段数码管显示
	
endmodule