flow_led.fit.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.140 ns register register " "Info: Estimated most critical path is register to register delay of 6.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[0\] 1 REG LAB_X8_Y12 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y12; Fanout = 3; REG Node = 'Cout\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[0] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.379 ns) + CELL(0.621 ns) 2.000 ns Add0~385 2 COMB LAB_X8_Y9 2 " "Info: 2: + IC(1.379 ns) + CELL(0.621 ns) = 2.000 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~385'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { Cout[0] Add0~385 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.086 ns Add0~387 3 COMB LAB_X8_Y9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 2.086 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~387'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~385 Add0~387 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.172 ns Add0~389 4 COMB LAB_X8_Y9 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 2.172 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~389'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~387 Add0~389 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.258 ns Add0~391 5 COMB LAB_X8_Y9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.258 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~391'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~389 Add0~391 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.344 ns Add0~393 6 COMB LAB_X8_Y9 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.344 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~393'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~391 Add0~393 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.430 ns Add0~395 7 COMB LAB_X8_Y9 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.430 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~395'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~393 Add0~395 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.516 ns Add0~397 8 COMB LAB_X8_Y9 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.516 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~397'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~395 Add0~397 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.602 ns Add0~399 9 COMB LAB_X8_Y9 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.602 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~399'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~397 Add0~399 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.688 ns Add0~401 10 COMB LAB_X8_Y9 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.688 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~401'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~399 Add0~401 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.774 ns Add0~403 11 COMB LAB_X8_Y9 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.774 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~403'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~401 Add0~403 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.860 ns Add0~405 12 COMB LAB_X8_Y9 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.860 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~405'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~403 Add0~405 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.946 ns Add0~407 13 COMB LAB_X8_Y9 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.946 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~407'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~405 Add0~407 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.032 ns Add0~409 14 COMB LAB_X8_Y9 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 3.032 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~409'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~407 Add0~409 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.118 ns Add0~411 15 COMB LAB_X8_Y9 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 3.118 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~411'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~409 Add0~411 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.204 ns Add0~413 16 COMB LAB_X8_Y9 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 3.204 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~413'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~411 Add0~413 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.290 ns Add0~415 17 COMB LAB_X8_Y9 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 3.290 ns; Loc. = LAB_X8_Y9; Fanout = 2; COMB Node = 'Add0~415'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~413 Add0~415 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.107 ns) + CELL(0.086 ns) 3.483 ns Add0~417 18 COMB LAB_X8_Y8 2 " "Info: 18: + IC(0.107 ns) + CELL(0.086 ns) = 3.483 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'Add0~417'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.193 ns" { Add0~415 Add0~417 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.569 ns Add0~419 19 COMB LAB_X8_Y8 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.569 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'Add0~419'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~417 Add0~419 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.655 ns Add0~421 20 COMB LAB_X8_Y8 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.655 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'Add0~421'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~419 Add0~421 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.741 ns Add0~423 21 COMB LAB_X8_Y8 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.741 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'Add0~423'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~421 Add0~423 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.827 ns Add0~425 22 COMB LAB_X8_Y8 2 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.827 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'Add0~425'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~423 Add0~425 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.913 ns Add0~427 23 COMB LAB_X8_Y8 2 " "Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.913 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'Add0~427'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~425 Add0~427 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.999 ns Add0~429 24 COMB LAB_X8_Y8 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.999 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'Add0~429'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~427 Add0~429 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.505 ns Add0~430 25 COMB LAB_X8_Y8 1 " "Info: 25: + IC(0.000 ns) + CELL(0.506 ns) = 4.505 ns; Loc. = LAB_X8_Y8; Fanout = 1; COMB Node = 'Add0~430'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~429 Add0~430 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(0.651 ns) 6.032 ns Cout~250 26 COMB LAB_X7_Y9 1 " "Info: 26: + IC(0.876 ns) + CELL(0.651 ns) = 6.032 ns; Loc. = LAB_X7_Y9; Fanout = 1; COMB Node = 'Cout~250'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { Add0~430 Cout~250 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.140 ns Cout\[23\] 27 REG LAB_X7_Y9 3 " "Info: 27: + IC(0.000 ns) + CELL(0.108 ns) = 6.140 ns; Loc. = LAB_X7_Y9; Fanout = 3; REG Node = 'Cout\[23\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Cout~250 Cout[23] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.778 ns ( 61.53 % ) " "Info: Total cell delay = 3.778 ns ( 61.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.362 ns ( 38.47 % ) " "Info: Total interconnect delay = 2.362 ns ( 38.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.140 ns" { Cout[0] Add0~385 Add0~387 Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~430 Cout~250 Cout[23] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X10_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}