📄 flow_led.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" { } { { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register Cout\[0\] register Cout\[23\] 160.88 MHz 6.216 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 160.88 MHz between source register \"Cout\[0\]\" and destination register \"Cout\[23\]\" (period= 6.216 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.933 ns + Longest register register " "Info: + Longest register to register delay is 5.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[0\] 1 REG LCFF_X8_Y12_N21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y12_N21; Fanout = 3; REG Node = 'Cout\[0\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[0] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.170 ns) + CELL(0.596 ns) 1.766 ns Add0~385 2 COMB LCCOMB_X8_Y9_N0 2 " "Info: 2: + IC(1.170 ns) + CELL(0.596 ns) = 1.766 ns; Loc. = LCCOMB_X8_Y9_N0; Fanout = 2; COMB Node = 'Add0~385'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.766 ns" { Cout[0] Add0~385 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.852 ns Add0~387 3 COMB LCCOMB_X8_Y9_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.852 ns; Loc. = LCCOMB_X8_Y9_N2; Fanout = 2; COMB Node = 'Add0~387'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~385 Add0~387 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.938 ns Add0~389 4 COMB LCCOMB_X8_Y9_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.938 ns; Loc. = LCCOMB_X8_Y9_N4; Fanout = 2; COMB Node = 'Add0~389'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~387 Add0~389 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.024 ns Add0~391 5 COMB LCCOMB_X8_Y9_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.024 ns; Loc. = LCCOMB_X8_Y9_N6; Fanout = 2; COMB Node = 'Add0~391'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~389 Add0~391 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.110 ns Add0~393 6 COMB LCCOMB_X8_Y9_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.110 ns; Loc. = LCCOMB_X8_Y9_N8; Fanout = 2; COMB Node = 'Add0~393'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~391 Add0~393 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.196 ns Add0~395 7 COMB LCCOMB_X8_Y9_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.196 ns; Loc. = LCCOMB_X8_Y9_N10; Fanout = 2; COMB Node = 'Add0~395'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~393 Add0~395 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.282 ns Add0~397 8 COMB LCCOMB_X8_Y9_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.282 ns; Loc. = LCCOMB_X8_Y9_N12; Fanout = 2; COMB Node = 'Add0~397'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~395 Add0~397 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 2.472 ns Add0~399 9 COMB LCCOMB_X8_Y9_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.190 ns) = 2.472 ns; Loc. = LCCOMB_X8_Y9_N14; Fanout = 2; COMB Node = 'Add0~399'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Add0~397 Add0~399 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.558 ns Add0~401 10 COMB LCCOMB_X8_Y9_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.558 ns; Loc. = LCCOMB_X8_Y9_N16; Fanout = 2; COMB Node = 'Add0~401'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~399 Add0~401 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.644 ns Add0~403 11 COMB LCCOMB_X8_Y9_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.644 ns; Loc. = LCCOMB_X8_Y9_N18; Fanout = 2; COMB Node = 'Add0~403'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~401 Add0~403 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.730 ns Add0~405 12 COMB LCCOMB_X8_Y9_N20 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.730 ns; Loc. = LCCOMB_X8_Y9_N20; Fanout = 2; COMB Node = 'Add0~405'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~403 Add0~405 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.816 ns Add0~407 13 COMB LCCOMB_X8_Y9_N22 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.816 ns; Loc. = LCCOMB_X8_Y9_N22; Fanout = 2; COMB Node = 'Add0~407'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~405 Add0~407 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.902 ns Add0~409 14 COMB LCCOMB_X8_Y9_N24 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.902 ns; Loc. = LCCOMB_X8_Y9_N24; Fanout = 2; COMB Node = 'Add0~409'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~407 Add0~409 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.988 ns Add0~411 15 COMB LCCOMB_X8_Y9_N26 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.988 ns; Loc. = LCCOMB_X8_Y9_N26; Fanout = 2; COMB Node = 'Add0~411'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~409 Add0~411 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.074 ns Add0~413 16 COMB LCCOMB_X8_Y9_N28 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 3.074 ns; Loc. = LCCOMB_X8_Y9_N28; Fanout = 2; COMB Node = 'Add0~413'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~411 Add0~413 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 3.249 ns Add0~415 17 COMB LCCOMB_X8_Y9_N30 2 " "Info: 17: + IC(0.000 ns) + CELL(0.175 ns) = 3.249 ns; Loc. = LCCOMB_X8_Y9_N30; Fanout = 2; COMB Node = 'Add0~415'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.175 ns" { Add0~413 Add0~415 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.335 ns Add0~417 18 COMB LCCOMB_X8_Y8_N0 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 3.335 ns; Loc. = LCCOMB_X8_Y8_N0; Fanout = 2; COMB Node = 'Add0~417'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~415 Add0~417 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.421 ns Add0~419 19 COMB LCCOMB_X8_Y8_N2 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.421 ns; Loc. = LCCOMB_X8_Y8_N2; Fanout = 2; COMB Node = 'Add0~419'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~417 Add0~419 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.507 ns Add0~421 20 COMB LCCOMB_X8_Y8_N4 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.507 ns; Loc. = LCCOMB_X8_Y8_N4; Fanout = 2; COMB Node = 'Add0~421'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~419 Add0~421 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.593 ns Add0~423 21 COMB LCCOMB_X8_Y8_N6 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.593 ns; Loc. = LCCOMB_X8_Y8_N6; Fanout = 2; COMB Node = 'Add0~423'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~421 Add0~423 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.679 ns Add0~425 22 COMB LCCOMB_X8_Y8_N8 2 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.679 ns; Loc. = LCCOMB_X8_Y8_N8; Fanout = 2; COMB Node = 'Add0~425'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~423 Add0~425 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.765 ns Add0~427 23 COMB LCCOMB_X8_Y8_N10 2 " "Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.765 ns; Loc. = LCCOMB_X8_Y8_N10; Fanout = 2; COMB Node = 'Add0~427'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~425 Add0~427 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.851 ns Add0~429 24 COMB LCCOMB_X8_Y8_N12 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.851 ns; Loc. = LCCOMB_X8_Y8_N12; Fanout = 2; COMB Node = 'Add0~429'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~427 Add0~429 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.357 ns Add0~430 25 COMB LCCOMB_X8_Y8_N14 1 " "Info: 25: + IC(0.000 ns) + CELL(0.506 ns) = 4.357 ns; Loc. = LCCOMB_X8_Y8_N14; Fanout = 1; COMB Node = 'Add0~430'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~429 Add0~430 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.370 ns) 5.825 ns Cout~250 26 COMB LCCOMB_X7_Y9_N30 1 " "Info: 26: + IC(1.098 ns) + CELL(0.370 ns) = 5.825 ns; Loc. = LCCOMB_X7_Y9_N30; Fanout = 1; COMB Node = 'Cout~250'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.468 ns" { Add0~430 Cout~250 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.933 ns Cout\[23\] 27 REG LCFF_X7_Y9_N31 3 " "Info: 27: + IC(0.000 ns) + CELL(0.108 ns) = 5.933 ns; Loc. = LCFF_X7_Y9_N31; Fanout = 3; REG Node = 'Cout\[23\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Cout~250 Cout[23] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.665 ns ( 61.77 % ) " "Info: Total cell delay = 3.665 ns ( 61.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.268 ns ( 38.23 % ) " "Info: Total interconnect delay = 2.268 ns ( 38.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.933 ns" { Cout[0] Add0~385 Add0~387 Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~430 Cout~250 Cout[23] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.933 ns" { Cout[0] {} Add0~385 {} Add0~387 {} Add0~389 {} Add0~391 {} Add0~393 {} Add0~395 {} Add0~397 {} Add0~399 {} Add0~401 {} Add0~403 {} Add0~405 {} Add0~407 {} Add0~409 {} Add0~411 {} Add0~413 {} Add0~415 {} Add0~417 {} Add0~419 {} Add0~421 {} Add0~423 {} Add0~425 {} Add0~427 {} Add0~429 {} Add0~430 {} Cout~250 {} Cout[23] {} } { 0.000ns 1.170ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.098ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.019 ns - Smallest " "Info: - Smallest clock skew is -0.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.821 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 2.821 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(0.666 ns) 2.821 ns Cout\[23\] 3 REG LCFF_X7_Y9_N31 3 " "Info: 3: + IC(0.876 ns) + CELL(0.666 ns) = 2.821 ns; Loc. = LCFF_X7_Y9_N31; Fanout = 3; REG Node = 'Cout\[23\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { Clk~clkctrl Cout[23] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.02 % ) " "Info: Total cell delay = 1.806 ns ( 64.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.015 ns ( 35.98 % ) " "Info: Total interconnect delay = 1.015 ns ( 35.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.821 ns" { Clk Clk~clkctrl Cout[23] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.821 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[23] {} } { 0.000ns 0.000ns 0.139ns 0.876ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.840 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 2.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(0.666 ns) 2.840 ns Cout\[0\] 3 REG LCFF_X8_Y12_N21 3 " "Info: 3: + IC(0.895 ns) + CELL(0.666 ns) = 2.840 ns; Loc. = LCFF_X8_Y12_N21; Fanout = 3; REG Node = 'Cout\[0\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { Clk~clkctrl Cout[0] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.59 % ) " "Info: Total cell delay = 1.806 ns ( 63.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.034 ns ( 36.41 % ) " "Info: Total interconnect delay = 1.034 ns ( 36.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { Clk Clk~clkctrl Cout[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[0] {} } { 0.000ns 0.000ns 0.139ns 0.895ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.821 ns" { Clk Clk~clkctrl Cout[23] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.821 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[23] {} } { 0.000ns 0.000ns 0.139ns 0.876ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { Clk Clk~clkctrl Cout[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[0] {} } { 0.000ns 0.000ns 0.139ns 0.895ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.933 ns" { Cout[0] Add0~385 Add0~387 Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~430 Cout~250 Cout[23] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.933 ns" { Cout[0] {} Add0~385 {} Add0~387 {} Add0~389 {} Add0~391 {} Add0~393 {} Add0~395 {} Add0~397 {} Add0~399 {} Add0~401 {} Add0~403 {} Add0~405 {} Add0~407 {} Add0~409 {} Add0~411 {} Add0~413 {} Add0~415 {} Add0~417 {} Add0~419 {} Add0~421 {} Add0~423 {} Add0~425 {} Add0~427 {} Add0~429 {} Add0~430 {} Cout~250 {} Cout[23] {} } { 0.000ns 1.170ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.098ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.821 ns" { Clk Clk~clkctrl Cout[23] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.821 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[23] {} } { 0.000ns 0.000ns 0.139ns 0.876ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { Clk Clk~clkctrl Cout[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[0] {} } { 0.000ns 0.000ns 0.139ns 0.895ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Led\[7\] Led\[7\]~reg0 8.567 ns register " "Info: tco from clock \"Clk\" to destination pin \"Led\[7\]\" through register \"Led\[7\]~reg0\" is 8.567 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.840 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 2.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(0.666 ns) 2.840 ns Led\[7\]~reg0 3 REG LCFF_X8_Y12_N15 1 " "Info: 3: + IC(0.895 ns) + CELL(0.666 ns) = 2.840 ns; Loc. = LCFF_X8_Y12_N15; Fanout = 1; REG Node = 'Led\[7\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { Clk~clkctrl Led[7]~reg0 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.59 % ) " "Info: Total cell delay = 1.806 ns ( 63.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.034 ns ( 36.41 % ) " "Info: Total interconnect delay = 1.034 ns ( 36.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { Clk Clk~clkctrl Led[7]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Led[7]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.895ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.423 ns + Longest register pin " "Info: + Longest register to pin delay is 5.423 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Led\[7\]~reg0 1 REG LCFF_X8_Y12_N15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y12_N15; Fanout = 1; REG Node = 'Led\[7\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Led[7]~reg0 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.137 ns) + CELL(3.286 ns) 5.423 ns Led\[7\] 2 PIN PIN_208 0 " "Info: 2: + IC(2.137 ns) + CELL(3.286 ns) = 5.423 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Led\[7\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.423 ns" { Led[7]~reg0 Led[7] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.286 ns ( 60.59 % ) " "Info: Total cell delay = 3.286 ns ( 60.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.137 ns ( 39.41 % ) " "Info: Total interconnect delay = 2.137 ns ( 39.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.423 ns" { Led[7]~reg0 Led[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.423 ns" { Led[7]~reg0 {} Led[7] {} } { 0.000ns 2.137ns } { 0.000ns 3.286ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { Clk Clk~clkctrl Led[7]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Led[7]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.895ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.423 ns" { Led[7]~reg0 Led[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.423 ns" { Led[7]~reg0 {} Led[7] {} } { 0.000ns 2.137ns } { 0.000ns 3.286ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
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