📄 prev_cmp_flow_led.qmsg
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 21:40:24 2008 " "Info: Processing started: Wed Jul 02 21:40:24 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Flow_Led -c Flow_Led " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Flow_Led -c Flow_Led" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Peak virtual memory: 152 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 21:40:27 2008 " "Info: Processing ended: Wed Jul 02 21:40:27 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 21:40:28 2008 " "Info: Processing started: Wed Jul 02 21:40:28 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Flow_Led -c Flow_Led --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Flow_Led -c Flow_Led --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" { } { { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register Cout\[6\] register Cout\[9\] 134.72 MHz 7.423 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 134.72 MHz between source register \"Cout\[6\]\" and destination register \"Cout\[9\]\" (period= 7.423 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.159 ns + Longest register register " "Info: + Longest register to register delay is 7.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[6\] 1 REG LCFF_X5_Y16_N13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y16_N13; Fanout = 3; REG Node = 'Cout\[6\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[6] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.667 ns) + CELL(0.529 ns) 3.196 ns Equal0~360 2 COMB LCCOMB_X10_Y6_N24 1 " "Info: 2: + IC(2.667 ns) + CELL(0.529 ns) = 3.196 ns; Loc. = LCCOMB_X10_Y6_N24; Fanout = 1; COMB Node = 'Equal0~360'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.196 ns" { Cout[6] Equal0~360 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.417 ns) + CELL(0.206 ns) 4.819 ns Equal0~362 3 COMB LCCOMB_X6_Y8_N16 12 " "Info: 3: + IC(1.417 ns) + CELL(0.206 ns) = 4.819 ns; Loc. = LCCOMB_X6_Y8_N16; Fanout = 12; COMB Node = 'Equal0~362'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.623 ns" { Equal0~360 Equal0~362 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.030 ns) + CELL(0.202 ns) 7.051 ns Cout~258 4 COMB LCCOMB_X3_Y18_N16 1 " "Info: 4: + IC(2.030 ns) + CELL(0.202 ns) = 7.051 ns; Loc. = LCCOMB_X3_Y18_N16; Fanout = 1; COMB Node = 'Cout~258'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { Equal0~362 Cout~258 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.159 ns Cout\[9\] 5 REG LCFF_X3_Y18_N17 3 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 7.159 ns; Loc. = LCFF_X3_Y18_N17; Fanout = 3; REG Node = 'Cout\[9\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Cout~258 Cout[9] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.045 ns ( 14.60 % ) " "Info: Total cell delay = 1.045 ns ( 14.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.114 ns ( 85.40 % ) " "Info: Total interconnect delay = 6.114 ns ( 85.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.159 ns" { Cout[6] Equal0~360 Equal0~362 Cout~258 Cout[9] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.159 ns" { Cout[6] {} Equal0~360 {} Equal0~362 {} Cout~258 {} Cout[9] {} } { 0.000ns 2.667ns 1.417ns 2.030ns 0.000ns } { 0.000ns 0.529ns 0.206ns 0.202ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.865 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns Cout\[9\] 3 REG LCFF_X3_Y18_N17 3 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X3_Y18_N17; Fanout = 3; REG Node = 'Cout\[9\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { Clk~clkctrl Cout[9] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { Clk Clk~clkctrl Cout[9] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[9] {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.865 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns Cout\[6\] 3 REG LCFF_X5_Y16_N13 3 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X5_Y16_N13; Fanout = 3; REG Node = 'Cout\[6\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { Clk~clkctrl Cout[6] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { Clk Clk~clkctrl Cout[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[6] {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { Clk Clk~clkctrl Cout[9] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[9] {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { Clk Clk~clkctrl Cout[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[6] {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.159 ns" { Cout[6] Equal0~360 Equal0~362 Cout~258 Cout[9] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.159 ns" { Cout[6] {} Equal0~360 {} Equal0~362 {} Cout~258 {} Cout[9] {} } { 0.000ns 2.667ns 1.417ns 2.030ns 0.000ns } { 0.000ns 0.529ns 0.206ns 0.202ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { Clk Clk~clkctrl Cout[9] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[9] {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { Clk Clk~clkctrl Cout[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[6] {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Led\[0\] Led\[0\]~reg0 8.039 ns register " "Info: tco from clock \"Clk\" to destination pin \"Led\[0\]\" through register \"Led\[0\]~reg0\" is 8.039 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.865 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 2.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.865 ns Led\[0\]~reg0 3 REG LCFF_X3_Y18_N1 1 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.865 ns; Loc. = LCFF_X3_Y18_N1; Fanout = 1; REG Node = 'Led\[0\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { Clk~clkctrl Led[0]~reg0 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.04 % ) " "Info: Total cell delay = 1.806 ns ( 63.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 36.96 % ) " "Info: Total interconnect delay = 1.059 ns ( 36.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { Clk Clk~clkctrl Led[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Led[0]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.870 ns + Longest register pin " "Info: + Longest register to pin delay is 4.870 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Led\[0\]~reg0 1 REG LCFF_X3_Y18_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X3_Y18_N1; Fanout = 1; REG Node = 'Led\[0\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Led[0]~reg0 } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.594 ns) + CELL(3.276 ns) 4.870 ns Led\[0\] 2 PIN PIN_193 0 " "Info: 2: + IC(1.594 ns) + CELL(3.276 ns) = 4.870 ns; Loc. = PIN_193; Fanout = 0; PIN Node = 'Led\[0\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.870 ns" { Led[0]~reg0 Led[0] } "NODE_NAME" } } { "Flow_Led.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Flow_Led/Flow_Led/Flow_Led.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.276 ns ( 67.27 % ) " "Info: Total cell delay = 3.276 ns ( 67.27 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.594 ns ( 32.73 % ) " "Info: Total interconnect delay = 1.594 ns ( 32.73 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.870 ns" { Led[0]~reg0 Led[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.870 ns" { Led[0]~reg0 {} Led[0] {} } { 0.000ns 1.594ns } { 0.000ns 3.276ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.865 ns" { Clk Clk~clkctrl Led[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.865 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Led[0]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.870 ns" { Led[0]~reg0 Led[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.870 ns" { Led[0]~reg0 {} Led[0] {} } { 0.000ns 1.594ns } { 0.000ns 3.276ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Peak virtual memory: 125 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 21:40:29 2008 " "Info: Processing ended: Wed Jul 02 21:40:29 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 12 s " "Info: Quartus II Full Compilation was successful. 0 errors, 12 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
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