flow_led.tan.rpt

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Jul 02 21:41:25 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Flow_Led -c Flow_Led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clk" is an undefined clock
Info: Clock "Clk" has Internal fmax of 160.88 MHz between source register "Cout[0]" and destination register "Cout[23]" (period= 6.216 ns)
    Info: + Longest register to register delay is 5.933 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y12_N21; Fanout = 3; REG Node = 'Cout[0]'
        Info: 2: + IC(1.170 ns) + CELL(0.596 ns) = 1.766 ns; Loc. = LCCOMB_X8_Y9_N0; Fanout = 2; COMB Node = 'Add0~385'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.852 ns; Loc. = LCCOMB_X8_Y9_N2; Fanout = 2; COMB Node = 'Add0~387'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.938 ns; Loc. = LCCOMB_X8_Y9_N4; Fanout = 2; COMB Node = 'Add0~389'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.024 ns; Loc. = LCCOMB_X8_Y9_N6; Fanout = 2; COMB Node = 'Add0~391'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 2.110 ns; Loc. = LCCOMB_X8_Y9_N8; Fanout = 2; COMB Node = 'Add0~393'
        Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.196 ns; Loc. = LCCOMB_X8_Y9_N10; Fanout = 2; COMB Node = 'Add0~395'
        Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.282 ns; Loc. = LCCOMB_X8_Y9_N12; Fanout = 2; COMB Node = 'Add0~397'
        Info: 9: + IC(0.000 ns) + CELL(0.190 ns) = 2.472 ns; Loc. = LCCOMB_X8_Y9_N14; Fanout = 2; COMB Node = 'Add0~399'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.558 ns; Loc. = LCCOMB_X8_Y9_N16; Fanout = 2; COMB Node = 'Add0~401'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.644 ns; Loc. = LCCOMB_X8_Y9_N18; Fanout = 2; COMB Node = 'Add0~403'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.730 ns; Loc. = LCCOMB_X8_Y9_N20; Fanout = 2; COMB Node = 'Add0~405'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.816 ns; Loc. = LCCOMB_X8_Y9_N22; Fanout = 2; COMB Node = 'Add0~407'
        Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.902 ns; Loc. = LCCOMB_X8_Y9_N24; Fanout = 2; COMB Node = 'Add0~409'
        Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.988 ns; Loc. = LCCOMB_X8_Y9_N26; Fanout = 2; COMB Node = 'Add0~411'
        Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 3.074 ns; Loc. = LCCOMB_X8_Y9_N28; Fanout = 2; COMB Node = 'Add0~413'
        Info: 17: + IC(0.000 ns) + CELL(0.175 ns) = 3.249 ns; Loc. = LCCOMB_X8_Y9_N30; Fanout = 2; COMB Node = 'Add0~415'
        Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 3.335 ns; Loc. = LCCOMB_X8_Y8_N0; Fanout = 2; COMB Node = 'Add0~417'
        Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.421 ns; Loc. = LCCOMB_X8_Y8_N2; Fanout = 2; COMB Node = 'Add0~419'
        Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.507 ns; Loc. = LCCOMB_X8_Y8_N4; Fanout = 2; COMB Node = 'Add0~421'
        Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.593 ns; Loc. = LCCOMB_X8_Y8_N6; Fanout = 2; COMB Node = 'Add0~423'
        Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.679 ns; Loc. = LCCOMB_X8_Y8_N8; Fanout = 2; COMB Node = 'Add0~425'
        Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.765 ns; Loc. = LCCOMB_X8_Y8_N10; Fanout = 2; COMB Node = 'Add0~427'
        Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.851 ns; Loc. = LCCOMB_X8_Y8_N12; Fanout = 2; COMB Node = 'Add0~429'
        Info: 25: + IC(0.000 ns) + CELL(0.506 ns) = 4.357 ns; Loc. = LCCOMB_X8_Y8_N14; Fanout = 1; COMB Node = 'Add0~430'
        Info: 26: + IC(1.098 ns) + CELL(0.370 ns) = 5.825 ns; Loc. = LCCOMB_X7_Y9_N30; Fanout = 1; COMB Node = 'Cout~250'
        Info: 27: + IC(0.000 ns) + CELL(0.108 ns) = 5.933 ns; Loc. = LCFF_X7_Y9_N31; Fanout = 3; REG Node = 'Cout[23]'
        Info: Total cell delay = 3.665 ns ( 61.77 % )
        Info: Total interconnect delay = 2.268 ns ( 38.23 % )
    Info: - Smallest clock skew is -0.019 ns
        Info: + Shortest clock path from clock "Clk" to destination register is 2.821 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'Clk~clkctrl'
            Info: 3: + IC(0.876 ns) + CELL(0.666 ns) = 2.821 ns; Loc. = LCFF_X7_Y9_N31; Fanout = 3; REG Node = 'Cout[23]'
            Info: Total cell delay = 1.806 ns ( 64.02 % )
            Info: Total interconnect delay = 1.015 ns ( 35.98 % )
        Info: - Longest clock path from clock "Clk" to source register is 2.840 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'Clk~clkctrl'
            Info: 3: + IC(0.895 ns) + CELL(0.666 ns) = 2.840 ns; Loc. = LCFF_X8_Y12_N21; Fanout = 3; REG Node = 'Cout[0]'
            Info: Total cell delay = 1.806 ns ( 63.59 % )
            Info: Total interconnect delay = 1.034 ns ( 36.41 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "Clk" to destination pin "Led[7]" through register "Led[7]~reg0" is 8.567 ns
    Info: + Longest clock path from clock "Clk" to source register is 2.840 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'Clk~clkctrl'
        Info: 3: + IC(0.895 ns) + CELL(0.666 ns) = 2.840 ns; Loc. = LCFF_X8_Y12_N15; Fanout = 1; REG Node = 'Led[7]~reg0'
        Info: Total cell delay = 1.806 ns ( 63.59 % )
        Info: Total interconnect delay = 1.034 ns ( 36.41 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.423 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y12_N15; Fanout = 1; REG Node = 'Led[7]~reg0'
        Info: 2: + IC(2.137 ns) + CELL(3.286 ns) = 5.423 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Led[7]'
        Info: Total cell delay = 3.286 ns ( 60.59 % )
        Info: Total interconnect delay = 2.137 ns ( 39.41 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Wed Jul 02 21:41:26 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01