segment2.tan.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register Cout\[1\] register Cout\[14\] 295.07 MHz 3.389 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 295.07 MHz between source register \"Cout\[1\]\" and destination register \"Cout\[14\]\" (period= 3.389 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.125 ns + Longest register register " "Info: + Longest register to register delay is 3.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[1\] 1 REG LCFF_X9_Y18_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y18_N5; Fanout = 2; REG Node = 'Cout\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[1] } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.754 ns) + CELL(0.621 ns) 1.375 ns Cout\[1\]~176 2 COMB LCCOMB_X9_Y18_N4 2 " "Info: 2: + IC(0.754 ns) + CELL(0.621 ns) = 1.375 ns; Loc. = LCCOMB_X9_Y18_N4; Fanout = 2; COMB Node = 'Cout\[1\]~176'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.375 ns" { Cout[1] Cout[1]~176 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.461 ns Cout\[2\]~178 3 COMB LCCOMB_X9_Y18_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.461 ns; Loc. = LCCOMB_X9_Y18_N6; Fanout = 2; COMB Node = 'Cout\[2\]~178'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[1]~176 Cout[2]~178 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.547 ns Cout\[3\]~180 4 COMB LCCOMB_X9_Y18_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.547 ns; Loc. = LCCOMB_X9_Y18_N8; Fanout = 2; COMB Node = 'Cout\[3\]~180'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[2]~178 Cout[3]~180 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.633 ns Cout\[4\]~182 5 COMB LCCOMB_X9_Y18_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.633 ns; Loc. = LCCOMB_X9_Y18_N10; Fanout = 2; COMB Node = 'Cout\[4\]~182'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[3]~180 Cout[4]~182 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.719 ns Cout\[5\]~184 6 COMB LCCOMB_X9_Y18_N12 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.719 ns; Loc. = LCCOMB_X9_Y18_N12; Fanout = 2; COMB Node = 'Cout\[5\]~184'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[4]~182 Cout[5]~184 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.909 ns Cout\[6\]~186 7 COMB LCCOMB_X9_Y18_N14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.190 ns) = 1.909 ns; Loc. = LCCOMB_X9_Y18_N14; Fanout = 2; COMB Node = 'Cout\[6\]~186'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Cout[5]~184 Cout[6]~186 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.995 ns Cout\[7\]~188 8 COMB LCCOMB_X9_Y18_N16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.995 ns; Loc. = LCCOMB_X9_Y18_N16; Fanout = 2; COMB Node = 'Cout\[7\]~188'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[6]~186 Cout[7]~188 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.081 ns Cout\[8\]~190 9 COMB LCCOMB_X9_Y18_N18 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.081 ns; Loc. = LCCOMB_X9_Y18_N18; Fanout = 2; COMB Node = 'Cout\[8\]~190'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[7]~188 Cout[8]~190 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.167 ns Cout\[9\]~192 10 COMB LCCOMB_X9_Y18_N20 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.167 ns; Loc. = LCCOMB_X9_Y18_N20; Fanout = 2; COMB Node = 'Cout\[9\]~192'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[8]~190 Cout[9]~192 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.253 ns Cout\[10\]~194 11 COMB LCCOMB_X9_Y18_N22 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.253 ns; Loc. = LCCOMB_X9_Y18_N22; Fanout = 2; COMB Node = 'Cout\[10\]~194'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[9]~192 Cout[10]~194 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.339 ns Cout\[11\]~196 12 COMB LCCOMB_X9_Y18_N24 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.339 ns; Loc. = LCCOMB_X9_Y18_N24; Fanout = 2; COMB Node = 'Cout\[11\]~196'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[10]~194 Cout[11]~196 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.425 ns Cout\[12\]~198 13 COMB LCCOMB_X9_Y18_N26 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.425 ns; Loc. = LCCOMB_X9_Y18_N26; Fanout = 2; COMB Node = 'Cout\[12\]~198'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[11]~196 Cout[12]~198 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.511 ns Cout\[13\]~200 14 COMB LCCOMB_X9_Y18_N28 1 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.511 ns; Loc. = LCCOMB_X9_Y18_N28; Fanout = 1; COMB Node = 'Cout\[13\]~200'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[12]~198 Cout[13]~200 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.017 ns Cout\[14\]~201 15 COMB LCCOMB_X9_Y18_N30 1 " "Info: 15: + IC(0.000 ns) + CELL(0.506 ns) = 3.017 ns; Loc. = LCCOMB_X9_Y18_N30; Fanout = 1; COMB Node = 'Cout\[14\]~201'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Cout[13]~200 Cout[14]~201 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.125 ns Cout\[14\] 16 REG LCFF_X9_Y18_N31 5 " "Info: 16: + IC(0.000 ns) + CELL(0.108 ns) = 3.125 ns; Loc. = LCFF_X9_Y18_N31; Fanout = 5; REG Node = 'Cout\[14\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Cout[14]~201 Cout[14] } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.371 ns ( 75.87 % ) " "Info: Total cell delay = 2.371 ns ( 75.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.754 ns ( 24.13 % ) " "Info: Total interconnect delay = 0.754 ns ( 24.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.125 ns" { Cout[1] Cout[1]~176 Cout[2]~178 Cout[3]~180 Cout[4]~182 Cout[5]~184 Cout[6]~186 Cout[7]~188 Cout[8]~190 Cout[9]~192 Cout[10]~194 Cout[11]~196 Cout[12]~198 Cout[13]~200 Cout[14]~201 Cout[14] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.125 ns" { Cout[1] {} Cout[1]~176 {} Cout[2]~178 {} Cout[3]~180 {} Cout[4]~182 {} Cout[5]~184 {} Cout[6]~186 {} Cout[7]~188 {} Cout[8]~190 {} Cout[9]~192 {} Cout[10]~194 {} Cout[11]~196 {} Cout[12]~198 {} Cout[13]~200 {} Cout[14]~201 {} Cout[14] {} } { 0.000ns 0.754ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.872 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'Clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.666 ns) 2.872 ns Cout\[14\] 3 REG LCFF_X9_Y18_N31 5 " "Info: 3: + IC(0.927 ns) + CELL(0.666 ns) = 2.872 ns; Loc. = LCFF_X9_Y18_N31; Fanout = 5; REG Node = 'Cout\[14\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.593 ns" { Clk~clkctrl Cout[14] } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.88 % ) " "Info: Total cell delay = 1.806 ns ( 62.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 37.12 % ) " "Info: Total interconnect delay = 1.066 ns ( 37.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Clk Clk~clkctrl Cout[14] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[14] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.872 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'Clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(0.666 ns) 2.872 ns Cout\[1\] 3 REG LCFF_X9_Y18_N5 2 " "Info: 3: + IC(0.927 ns) + CELL(0.666 ns) = 2.872 ns; Loc. = LCFF_X9_Y18_N5; Fanout = 2; REG Node = 'Cout\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.593 ns" { Clk~clkctrl Cout[1] } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.88 % ) " "Info: Total cell delay = 1.806 ns ( 62.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 37.12 % ) " "Info: Total interconnect delay = 1.066 ns ( 37.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Clk Clk~clkctrl Cout[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[1] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Clk Clk~clkctrl Cout[14] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[14] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Clk Clk~clkctrl Cout[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[1] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.125 ns" { Cout[1] Cout[1]~176 Cout[2]~178 Cout[3]~180 Cout[4]~182 Cout[5]~184 Cout[6]~186 Cout[7]~188 Cout[8]~190 Cout[9]~192 Cout[10]~194 Cout[11]~196 Cout[12]~198 Cout[13]~200 Cout[14]~201 Cout[14] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.125 ns" { Cout[1] {} Cout[1]~176 {} Cout[2]~178 {} Cout[3]~180 {} Cout[4]~182 {} Cout[5]~184 {} Cout[6]~186 {} Cout[7]~188 {} Cout[8]~190 {} Cout[9]~192 {} Cout[10]~194 {} Cout[11]~196 {} Cout[12]~198 {} Cout[13]~200 {} Cout[14]~201 {} Cout[14] {} } { 0.000ns 0.754ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Clk Clk~clkctrl Cout[14] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[14] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.872 ns" { Clk Clk~clkctrl Cout[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.872 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[1] {} } { 0.000ns 0.000ns 0.139ns 0.927ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Sev_Seg_Led_Sel_n\[0\] Sev_Seg_Led_Sel_n\[0\]~reg0 8.294 ns register " "Info: tco from clock \"Clk\" to destination pin \"Sev_Seg_Led_Sel_n\[0\]\" through register \"Sev_Seg_Led_Sel_n\[0\]~reg0\" is 8.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.873 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 2.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 25 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'Clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.928 ns) + CELL(0.666 ns) 2.873 ns Sev_Seg_Led_Sel_n\[0\]~reg0 3 REG LCFF_X10_Y18_N1 5 " "Info: 3: + IC(0.928 ns) + CELL(0.666 ns) = 2.873 ns; Loc. = LCFF_X10_Y18_N1; Fanout = 5; REG Node = 'Sev_Seg_Led_Sel_n\[0\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { Clk~clkctrl Sev_Seg_Led_Sel_n[0]~reg0 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 28 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.86 % ) " "Info: Total cell delay = 1.806 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.067 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.067 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { Clk Clk~clkctrl Sev_Seg_Led_Sel_n[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.873 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Sev_Seg_Led_Sel_n[0]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 28 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.117 ns + Longest register pin " "Info: + Longest register to pin delay is 5.117 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Sev_Seg_Led_Sel_n\[0\]~reg0 1 REG LCFF_X10_Y18_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y18_N1; Fanout = 5; REG Node = 'Sev_Seg_Led_Sel_n\[0\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sev_Seg_Led_Sel_n[0]~reg0 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 28 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.851 ns) + CELL(3.266 ns) 5.117 ns Sev_Seg_Led_Sel_n\[0\] 2 PIN PIN_181 0 " "Info: 2: + IC(1.851 ns) + CELL(3.266 ns) = 5.117 ns; Loc. = PIN_181; Fanout = 0; PIN Node = 'Sev_Seg_Led_Sel_n\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.117 ns" { Sev_Seg_Led_Sel_n[0]~reg0 Sev_Seg_Led_Sel_n[0] } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.266 ns ( 63.83 % ) " "Info: Total cell delay = 3.266 ns ( 63.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.851 ns ( 36.17 % ) " "Info: Total interconnect delay = 1.851 ns ( 36.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.117 ns" { Sev_Seg_Led_Sel_n[0]~reg0 Sev_Seg_Led_Sel_n[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.117 ns" { Sev_Seg_Led_Sel_n[0]~reg0 {} Sev_Seg_Led_Sel_n[0] {} } { 0.000ns 1.851ns } { 0.000ns 3.266ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { Clk Clk~clkctrl Sev_Seg_Led_Sel_n[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.873 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Sev_Seg_Led_Sel_n[0]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.117 ns" { Sev_Seg_Led_Sel_n[0]~reg0 Sev_Seg_Led_Sel_n[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.117 ns" { Sev_Seg_Led_Sel_n[0]~reg0 {} Sev_Seg_Led_Sel_n[0] {} } { 0.000ns 1.851ns } { 0.000ns 3.266ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Peak virtual memory: 125 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 22:08:21 2008 " "Info: Processing ended: Wed Jul 02 22:08:21 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}