segment2.fit.qmsg

采用Altera公司的CycloneII芯片EP2C8的一些程序代码。

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.917 ns register register " "Info: Estimated most critical path is register to register delay of 2.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[0\] 1 REG LAB_X9_Y18 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y18; Fanout = 3; REG Node = 'Cout\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[0] } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.596 ns) 1.271 ns Cout\[1\]~176 2 COMB LAB_X9_Y18 2 " "Info: 2: + IC(0.675 ns) + CELL(0.596 ns) = 1.271 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[1\]~176'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { Cout[0] Cout[1]~176 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.357 ns Cout\[2\]~178 3 COMB LAB_X9_Y18 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.357 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[2\]~178'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[1]~176 Cout[2]~178 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.443 ns Cout\[3\]~180 4 COMB LAB_X9_Y18 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.443 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[3\]~180'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[2]~178 Cout[3]~180 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.529 ns Cout\[4\]~182 5 COMB LAB_X9_Y18 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.529 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[4\]~182'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[3]~180 Cout[4]~182 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.615 ns Cout\[5\]~184 6 COMB LAB_X9_Y18 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.615 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[5\]~184'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[4]~182 Cout[5]~184 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.701 ns Cout\[6\]~186 7 COMB LAB_X9_Y18 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.701 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[6\]~186'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[5]~184 Cout[6]~186 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.787 ns Cout\[7\]~188 8 COMB LAB_X9_Y18 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.787 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[7\]~188'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[6]~186 Cout[7]~188 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.873 ns Cout\[8\]~190 9 COMB LAB_X9_Y18 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.873 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[8\]~190'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[7]~188 Cout[8]~190 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.959 ns Cout\[9\]~192 10 COMB LAB_X9_Y18 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.959 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[9\]~192'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[8]~190 Cout[9]~192 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.045 ns Cout\[10\]~194 11 COMB LAB_X9_Y18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.045 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[10\]~194'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[9]~192 Cout[10]~194 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.131 ns Cout\[11\]~196 12 COMB LAB_X9_Y18 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.131 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[11\]~196'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[10]~194 Cout[11]~196 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.217 ns Cout\[12\]~198 13 COMB LAB_X9_Y18 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.217 ns; Loc. = LAB_X9_Y18; Fanout = 2; COMB Node = 'Cout\[12\]~198'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[11]~196 Cout[12]~198 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.303 ns Cout\[13\]~200 14 COMB LAB_X9_Y18 1 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.303 ns; Loc. = LAB_X9_Y18; Fanout = 1; COMB Node = 'Cout\[13\]~200'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[12]~198 Cout[13]~200 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.809 ns Cout\[14\]~201 15 COMB LAB_X9_Y18 1 " "Info: 15: + IC(0.000 ns) + CELL(0.506 ns) = 2.809 ns; Loc. = LAB_X9_Y18; Fanout = 1; COMB Node = 'Cout\[14\]~201'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Cout[13]~200 Cout[14]~201 } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.917 ns Cout\[14\] 16 REG LAB_X9_Y18 5 " "Info: 16: + IC(0.000 ns) + CELL(0.108 ns) = 2.917 ns; Loc. = LAB_X9_Y18; Fanout = 5; REG Node = 'Cout\[14\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Cout[14]~201 Cout[14] } "NODE_NAME" } } { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.242 ns ( 76.86 % ) " "Info: Total cell delay = 2.242 ns ( 76.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.675 ns ( 23.14 % ) " "Info: Total interconnect delay = 0.675 ns ( 23.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.917 ns" { Cout[0] Cout[1]~176 Cout[2]~178 Cout[3]~180 Cout[4]~182 Cout[5]~184 Cout[6]~186 Cout[7]~188 Cout[8]~190 Cout[9]~192 Cout[10]~194 Cout[11]~196 Cout[12]~198 Cout[13]~200 Cout[14]~201 Cout[14] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y10 X10_Y19 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y10 to location X10_Y19" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}