📄 segment2.map.qmsg
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{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Segment2\|Disp_Sel " "Info: Selected Auto state machine encoding method for state machine \"\|Segment2\|Disp_Sel\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Segment2\|Disp_Sel " "Info: Encoding result for state machine \"\|Segment2\|Disp_Sel\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "16 " "Info: Completed encoding using 16 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.1111 " "Info: Encoded state bit \"Disp_Sel.1111\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.1110 " "Info: Encoded state bit \"Disp_Sel.1110\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.1101 " "Info: Encoded state bit \"Disp_Sel.1101\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.1100 " "Info: Encoded state bit \"Disp_Sel.1100\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.1011 " "Info: Encoded state bit \"Disp_Sel.1011\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.1010 " "Info: Encoded state bit \"Disp_Sel.1010\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.1001 " "Info: Encoded state bit \"Disp_Sel.1001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.1000 " "Info: Encoded state bit \"Disp_Sel.1000\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 28 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.0111 " "Info: Encoded state bit \"Disp_Sel.0111\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.0110 " "Info: Encoded state bit \"Disp_Sel.0110\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.0101 " "Info: Encoded state bit \"Disp_Sel.0101\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.0100 " "Info: Encoded state bit \"Disp_Sel.0100\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.0011 " "Info: Encoded state bit \"Disp_Sel.0011\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.0010 " "Info: Encoded state bit \"Disp_Sel.0010\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.0001 " "Info: Encoded state bit \"Disp_Sel.0001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Disp_Sel.0000 " "Info: Encoded state bit \"Disp_Sel.0000\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0 0} } { } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.0000 0000000000000000 " "Info: State \"\|Segment2\|Disp_Sel.0000\" uses code string \"0000000000000000\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.0001 0000000000000011 " "Info: State \"\|Segment2\|Disp_Sel.0001\" uses code string \"0000000000000011\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.0010 0000000000000101 " "Info: State \"\|Segment2\|Disp_Sel.0010\" uses code string \"0000000000000101\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.0011 0000000000001001 " "Info: State \"\|Segment2\|Disp_Sel.0011\" uses code string \"0000000000001001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.0100 0000000000010001 " "Info: State \"\|Segment2\|Disp_Sel.0100\" uses code string \"0000000000010001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.0101 0000000000100001 " "Info: State \"\|Segment2\|Disp_Sel.0101\" uses code string \"0000000000100001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.0110 0000000001000001 " "Info: State \"\|Segment2\|Disp_Sel.0110\" uses code string \"0000000001000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.0111 0000000010000001 " "Info: State \"\|Segment2\|Disp_Sel.0111\" uses code string \"0000000010000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.1000 0000000100000001 " "Info: State \"\|Segment2\|Disp_Sel.1000\" uses code string \"0000000100000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 28 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.1001 0000001000000001 " "Info: State \"\|Segment2\|Disp_Sel.1001\" uses code string \"0000001000000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.1010 0000010000000001 " "Info: State \"\|Segment2\|Disp_Sel.1010\" uses code string \"0000010000000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.1011 0000100000000001 " "Info: State \"\|Segment2\|Disp_Sel.1011\" uses code string \"0000100000000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.1100 0001000000000001 " "Info: State \"\|Segment2\|Disp_Sel.1100\" uses code string \"0001000000000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.1101 0010000000000001 " "Info: State \"\|Segment2\|Disp_Sel.1101\" uses code string \"0010000000000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.1110 0100000000000001 " "Info: State \"\|Segment2\|Disp_Sel.1110\" uses code string \"0100000000000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Segment2\|Disp_Sel.1111 1000000000000001 " "Info: State \"\|Segment2\|Disp_Sel.1111\" uses code string \"1000000000000001\"" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0 0} } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "Disp_Sel.0001 Sev_Seg_Led_Sel_n\[0\]~reg0 " "Info (13360): Duplicate register \"Disp_Sel.0001\" merged to single register \"Sev_Seg_Led_Sel_n\[0\]~reg0\", power-up level changed" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 13360 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "Disp_Sel.0010 Sev_Seg_Led_Sel_n\[1\]~reg0 " "Info (13360): Duplicate register \"Disp_Sel.0010\" merged to single register \"Sev_Seg_Led_Sel_n\[1\]~reg0\", power-up level changed" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 13360 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "Disp_Sel.0011 Sev_Seg_Led_Sel_n\[2\]~reg0 " "Info (13360): Duplicate register \"Disp_Sel.0011\" merged to single register \"Sev_Seg_Led_Sel_n\[2\]~reg0\", power-up level changed" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 13360 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "Disp_Sel.0100 Sev_Seg_Led_Sel_n\[3\]~reg0 " "Info (13360): Duplicate register \"Disp_Sel.0100\" merged to single register \"Sev_Seg_Led_Sel_n\[3\]~reg0\", power-up level changed" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } } } 0 13360 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0 0} } { } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Data_n\[1\] GND " "Warning (13410): Pin \"Sev_Seg_Led_Data_n\[1\]\" is stuck at GND" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 47 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Sev_Seg_Led_Data_n\[7\] GND " "Warning (13410): Pin \"Sev_Seg_Led_Data_n\[7\]\" is stuck at GND" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 47 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Led_En_n VCC " "Warning (13410): Pin \"Led_En_n\" is stuck at VCC" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 14 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Buzz GND " "Warning (13410): Pin \"Buzz\" is stuck at GND" { } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 16 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "30 30 " "Info: 30 registers lost all their fanouts during netlist optimizations. The first 30 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.0110 " "Info: Register \"Disp_Sel.0110\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.1000 " "Info: Register \"Disp_Sel.1000\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.1011 " "Info: Register \"Disp_Sel.1011\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.0101 " "Info: Register \"Disp_Sel.0101\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.0111 " "Info: Register \"Disp_Sel.0111\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.1001 " "Info: Register \"Disp_Sel.1001\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.1010 " "Info: Register \"Disp_Sel.1010\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.1100 " "Info: Register \"Disp_Sel.1100\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.1101 " "Info: Register \"Disp_Sel.1101\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.1110 " "Info: Register \"Disp_Sel.1110\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel.1111 " "Info: Register \"Disp_Sel.1111\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel~7 " "Info: Register \"Disp_Sel~7\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel~8 " "Info: Register \"Disp_Sel~8\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel~9 " "Info: Register \"Disp_Sel~9\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Disp_Sel~10 " "Info: Register \"Disp_Sel~10\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[15\] " "Info: Register \"Cout\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[16\] " "Info: Register \"Cout\[16\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[17\] " "Info: Register \"Cout\[17\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[18\] " "Info: Register \"Cout\[18\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[19\] " "Info: Register \"Cout\[19\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[20\] " "Info: Register \"Cout\[20\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[21\] " "Info: Register \"Cout\[21\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[22\] " "Info: Register \"Cout\[22\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[23\] " "Info: Register \"Cout\[23\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[24\] " "Info: Register \"Cout\[24\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[25\] " "Info: Register \"Cout\[25\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[26\] " "Info: Register \"Cout\[26\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[27\] " "Info: Register \"Cout\[27\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[28\] " "Info: Register \"Cout\[28\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "Cout\[29\] " "Info: Register \"Cout\[29\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Info: Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Info: Implemented 14 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "25 " "Info: Implemented 25 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Peak virtual memory: 156 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 02 22:08:06 2008 " "Info: Processing ended: Wed Jul 02 22:08:06 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
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