bcd2seg.v

来自「也就是乐透彩票模拟程序用为verilogHDL描述」· Verilog 代码 · 共 21 行

module seg7dec (output reg g, f, e, d, c, b, a, 
					input [3:0] bcdin);

always @ (bcdin)
begin  
	case (bcdin) //coding assumes active-high leds
		0 : {g, f, e, d, c, b, a} = 7'b0111111;
		1 : {g, f, e, d, c, b, a} = 7'b0000110;
		2 : {g, f, e, d, c, b, a} = 7'b1011011;
		3 : {g, f, e, d, c, b, a} = 7'b1001111;
		4 : {g, f, e, d, c, b, a} = 7'b1100110;
		5 : {g, f, e, d, c, b, a} = 7'b1101101;
		6 : {g, f, e, d, c, b, a} = 7'b1111101;
		7 : {g, f, e, d, c, b, a} = 7'b0000111;
		8 : {g, f, e, d, c, b, a} = 7'b1111111;
		9 : {g, f, e, d, c, b, a} = 7'b1101111;
		default : {g, f, e, d, c, b, a} = 7'bx;
	endcase
end 

endmodule