lottery3.v

也就是乐透彩票模拟程序用为verilogHDL描述

//verilog description of a lucky dip machine 
//compatible with Digilent X-Board 
//see ucf file for pin allocations

module Lottery3(input clock, 
					input reset, 
					input next_no, //chooses next random number
					output AA, AB, AC, AD, AE, AF, AG, //7-segment outputs (muxed)
					output reg [5:0] NumLed,  //individual number LEDs
					output CAT);  //common cathode

wire match;
wire next_no_p;

//fast 1->49 counter
wire [7:0] count1to49;  

//memory to hold six lottery numbers
reg [7:0] lottmem [0:5];

//register to hold current lottery number
reg [7:0] display;

//muxed BCD codes
wire [3:0] disp_BCD;  

//1-to-49 free-running counter
count49 counter(count1to49, clock, reset);

//check current count against first 5 numbers
assign match = (count1to49 == lottmem[0])||
				(count1to49 == lottmem[1])||
				(count1to49 == lottmem[2])||
				(count1to49 == lottmem[3])||
				(count1to49 == lottmem[4]);


//flip-flops and gate to generate 'next_no_p'
dff dff0(q0, next_no, clock);
dff dff1(q1, q0, clock);

assign next_no_p = ~q0 & q1;

reg [2:0] selnum, count;

//memory control
always @(posedge clock or posedge reset)
begin : memcon

	integer i;
	
	if (reset == 1'b1)
		begin
			for (i = 0; i < 6; i = i + 1)
					lottmem[i] <= 0;  //reset the memory
			selnum <= 0;
			count <= 0;
			display <= 8'b0;
			NumLed <= 6'b111111;  //turn off all LEDs
		end
	else if (next_no_p)	
		begin		
			if (count == 6) //just display numbers if 6 chosen already
				display <= lottmem[selnum];
			else if (!match) //choose a new random number 
				begin
					lottmem[selnum] <= count1to49;
					display <= count1to49;
					count <= count + 1;
					NumLed[selnum] <= 1'b0; //turn on one LED
				end
			if (selnum == 5)
				selnum <= 0;
			else
				selnum <= selnum + 1;				
		end
		
end


//8-bit counter for display mux	
reg [7:0] dcnt;
		
always @(posedge clock or posedge reset)
		dcnt <= (reset == 1'b1)? 0 : dcnt + 1;

//mux for upper and lower BCD digits		
assign disp_BCD = (dcnt[7] == 1'b1)?  display[7:4] : display[3:0];

//bcd to 7-segment decoder for display
seg7dec decoder(.a(AA), .b(AB), .c(AC), 
							.d(AD), .e(AE), .f(AF), .g(AG), 
							.bcdin(disp_BCD));

//active low common cathodes
assign CAT = dcnt[7];  	

endmodule