testlott3.v

来自「也就是乐透彩票模拟程序用为verilogHDL描述」· Verilog 代码 · 共 82 行

//test module for lottery lucky dip machine

`timescale 1 ns/1 ns

module test_lottery3;

//inputs
reg CLK, RST, NEXT;

//7-segment outputs
wire AA, AB, AC, AD, AE, AF, AG;

wire [5:0] NumLed;

//common cathode output
wire CAT; 

//clock generator
initial
begin : clk_gen
	CLK = 1'b0;
	forever
		#50 CLK = ~CLK;
end

initial begin : stim
	
	RST = 1'b1;   //reset the system
	NEXT = 1'b1;  
  repeat(4) @(negedge CLK); //wait for 4 clocks
	RST = 1'b0;
    
	//generate 12 next_no pulses
	repeat (12) begin
		repeat(17) @(negedge CLK); 
		NEXT = 1'b0;
		repeat(3) @(negedge CLK); 
		NEXT = 1'b1;  
  end
	
	repeat(5) @(negedge CLK); //wait for 5 clocks
	RST = 1'b1;   //reset the system  
  repeat(4) @(negedge CLK);
	RST = 1'b0;
    
	//generate another 12 next_no pulses
	repeat (12) begin
		repeat(17) @(negedge CLK); 
		NEXT = 1'b0;
		repeat(3) @(negedge CLK);
		NEXT = 1'b1;  
  end
	
	repeat(4) @(negedge CLK);
	RST = 1'b1;   //reset the system  
  repeat(4) @(negedge CLK);
	RST = 1'b0;
	//following sequence indicates what happens if the same number is selected
	
	repeat (6) begin
		repeat(40) @(negedge CLK); 
		NEXT = 1'b0;
		repeat(9) @(negedge CLK);
		NEXT = 1'b1;  
  end
	$stop;
	
end	

//instantiate module-under-test (comment one out)
/*Lottery3 UUT(.clock(CLK), .reset(RST), .next_no(NEXT), //.segh(SEGH), 
								.AA(AA), .AB(AB),.AC(AC),.AD(AD),
								.AE(AE),.AF(AF),.AG(AG),
								.NumLed(NumLed),.CAT(CAT));*/
								
Lottery3_simple UUT(.clock(CLK), .reset(RST), .next_no(NEXT), //.segh(SEGH), 
								.AA(AA), .AB(AB),.AC(AC),.AD(AD),
								.AE(AE),.AF(AF),.AG(AG),
								.NumLed(NumLed),.CAT(CAT));								

endmodule