lottery3.ucf

也就是乐透彩票模拟程序用为verilogHDL描述

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "AA"  LOC = "P82"  ; 
NET "AB"  LOC = "P81"  ; 
NET "AC"  LOC = "P80"  ; 
NET "AD"  LOC = "P79"  ; 
NET "AE"  LOC = "P78"  ; 
NET "AF"  LOC = "P77"  ; 
NET "AG"  LOC = "P76"  ; 
NET "CAT"  LOC = "P75"  ; 
NET "clock"  LOC = "P38"  ; 
NET "next_no"  LOC = "P60"  ; 
NET "NumLed<0>"  LOC = "P86"  ;
NET "NumLed<1>"  LOC = "P52"  ;
NET "NumLed<2>"  LOC = "P26"  ;
NET "NumLed<3>"  LOC = "P88"  ;
NET "NumLed<4>"  LOC = "P131"  ;
NET "NumLed<5>"  LOC = "P6"  ;
NET "reset"  LOC = "P61"  ; 

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE