count49.v

来自「也就是乐透彩票模拟程序用为verilogHDL描述」· Verilog 代码 · 共 18 行

//a lottery number counter 
//counts from 01 -> 49 in BCD format

module count49 (output reg [7:0] cnt1to49, 
					input clock, clear);

always @(posedge clock)
begin
   if (clear || cnt1to49 == 8'h49)
      cnt1to49 <= 8'h1;
   else if (cnt1to49[3:0] == 9)
      cnt1to49 <= cnt1to49 + (16 - 9);
   else
      cnt1to49[3:0] <= cnt1to49[3:0] + 1;      
end

endmodule