lottery3_simple.v

也就是乐透彩票模拟程序用为verilogHDL描述

//verilog description of a lucky dip machine (simple version, no memory)
//compatible with Digilent X-Board 
//see ucf file for pin allocations

module Lottery3_simple(input clock, 
					input reset, 
					input next_no, //chooses next random number
					output AA, AB, AC, AD, AE, AF, AG, //7-segment outputs (muxed)
					output reg [5:0] NumLed,  //individual number LEDs
					output CAT);  //common cathode

wire next_no_p;

//fast 1->49 counter
wire [7:0] count1to49;  

//register to hold current lottery number (sampled from counter)
reg [7:0] display;

//muxed BCD codes
wire [3:0] disp_BCD;  

//1-to-49 free-running counter 
count49 counter(.cnt1to49(count1to49), 
						.clock(clock), 
						.clear(reset));


//flip-flops and gate to generate 'next_no_p'
dff dff0(q0, next_no, clock);
dff dff1(q1, q0, clock);

assign next_no_p = ~q0 & q1;

//sequential logic to sample fast counter and activate leds
always @(posedge clock or posedge reset)
begin	
	if (reset == 1'b1)
		begin
			display <= 8'b0;
			NumLed <= 6'b111111;  //turn off leds
		end
	else if (next_no_p)	
		begin		
			display <= count1to49;   //pick random number from counter
			NumLed <= {NumLed[4:0], 1'b0}; //light leds
		end		
end


//8-bit counter for display mux	
reg [7:0] dcnt;
		
always @(posedge clock or posedge reset)
		dcnt <= (reset == 1'b1)? 0 : dcnt + 1;

//mux for upper and lower BCD digits		
assign disp_BCD = (dcnt[7] == 1'b1)?  display[7:4] : display[3:0];

//bcd to 7-segment decoder for display
seg7dec decoder(.a(AA), .b(AB), .c(AC), 
							.d(AD), .e(AE), .f(AF), .g(AG), 
							.bcdin(disp_BCD));

//active low common cathodes
assign CAT = dcnt[7];  	

endmodule