📄 minit.s
字号:
;//////////////////////////////////////////////////////
; INIT.s
; EP7312 Processor Start Up Assembly Code File.
; Fantasy Studio ZX 03.14.2004
;//////////////////////////////////////////////////////
;Boot From FlashROM
FBADDR EQU 0x00000000 ;Flash ROM Base Address 8-Bit 512KBytes
IBADDR EQU 0x60000000 ;Internal SRAM Base Address 32-Bit 48'400 Bytes CS[6]
;IBADDR EQU 0x10001000 ;Internal SRAM Base Address 32-Bit 48'400 Bytes CS[6]
BBADDR EQU 0x70000000 ;Boot ROM Address 32-Bit 128 Bytes CS[7]
SBADDR EQU 0x80000000 ;Internal Registers Base Address 32-Bit 16KBytes
DBADDR EQU 0xC0000000 ;SDRAM Base Address 32-Bit 32MBytes
;Stack Size
_SVC_STKSIZE EQU 1024*1
_UND_STKSIZE EQU 256
_ABT_STKSIZE EQU 256
_IRQ_STKSIZE EQU 256
_FIQ_STKSIZE EQU 256
_USE_STKSIZE EQU 1024
;Interrupt Control
rMEMCFG1 EQU SBADDR+0x0180
rMEMCFG2 EQU SBADDR+0x01C0
rINTMR1 EQU SBADDR+0x0280
rINTMR2 EQU SBADDR+0x1280
rINTSR1 EQU SBADDR+0x0240
rINTSR2 EQU SBADDR+0x1240
rSDCONF EQU SBADDR+0x2300
rSDRFPR EQU SBADDR+0x2340
rSYSCON2 EQU SBADDR+0x1100
rSYSCON3 EQU SBADDR+0x2200
;Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
ldr pc,=$HandleLabel
MEND
;Program Start
AREA |Assembly$$code|, CODE, READONLY
ENTRY
;Interrupt Table In FlashROM
b ResetHandler ;for debug
b HandlerUndef ;handlerUndef
b HandlerSWI ;SWI interrupt handler
b HandlerPabort ;handlerPAbort
b HandlerDabort ;handlerDAbort
b . ;handlerReserved
; b HandlerIRQ ;handlerIRQ
b IRQHandler ;handlerIRQ
b HandlerFIQ ;handlerFIQ
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
IRQHandler
stmfd sp!,{r0-r12,lr}
; ldrb r2,[r12,#0x3]
; eor r2,r2,#0x01
; strb r2,[r12,#0x3]
; IMPORT t1_irq
; bl t1_irq
bl t1_irq_asm
ldr r12,=0x80000000
mov r2,#0xffffffff
str r2,[r12,#0x06c0]
ldmfd sp!,{r0-r12,lr}
subs pc,lr,#4
t1_irq_asm
ldr r12,=0x80000000
ldrb r2,[r12,#0x3]
eor r2,r2,#0x01
strb r2,[r12,#0x3]
mov pc,lr
;*****************************************************************************
;
; ResetHandler is the startup code to be used
;
;*****************************************************************************
ResetHandler
ldr r12,=0x80000000
ldrb r2,[r12,#0x3]
eor r2,r2,#0x01
strb r2,[r12,#0x3]
ldr r0,=0x00000070 ; Setup the MMU for 32 bit code and data.
mcr p15,0,r0,c1,c0,0
;------------------------------------------------------------------------
ldr r0,=0x00000000 ; Disable all interrupts
ldr r12,=rINTMR1
str r0,[r12] ; INTMR1 = 0x8000.0280
ldr r12,=rINTMR2
str r0,[r12] ; INTMR2 = 0x8000.1280
;-------------------------------------------------------------------------
DRAMControlvalue EQU 0x00000522 ; CASLAT=3, SDSIZE=256Mb, SDWIDTH=16, CLKCTL=0, SDACTIVE=1
DRAMConfigvalue EQU 0x00000100 ; REFRATE=7.11uS at 36MHz BCLK
ldr r1,=DRAMControlvalue ; Enable SDRAM Bank 0 and Bank 1 for EP73xx
ldr r12,=rSDCONF
str r1,[r12] ; store in SDCONF
ldr r1,=DRAMConfigvalue
ldr r12,=rSDRFPR
str r1,[r12] ; store in SDRFPR
ldr r12,=rSYSCON2 ; SDRAMZ = 0 32-Bit SDRAM
str r0,[r12] ; init syscon2 register at 0x8000.1100
;--------------------------------------------------------------------------
ldr r1,=0x06 ; Set bits 1:2 in SYSCON3 for 73.728 MHz clock Speed
ldr r12,=rSYSCON3
str r1,[r12] ; init syscon3 register at 0x8000.2200
;---------------------------------------------------------------------------
; Now configure the MemConfig register to get the following:
; nCS0 = NOR FLASH, 8-bit, 15 wait states
; nCS1 = Unused
; nCS2 = Unused
; nCS3 = Unused
; nCS4 = Unused
; nCS5 = Unused
MemConfig1value EQU 0x00050004
MemConfig2value EQU 0x00000000 ; boot rom and internal SRAM are ignored
ldr r1,=MemConfig1value ; configure nCS0-nCS3
ldr r12,=rMEMCFG1
str r1,[r12] ; MEMCFG1 = 0x8000.0180
ldr r1,=MemConfig2value ; configure nCS4 &nCS5
ldr r12,=rMEMCFG2
str r1,[r12] ; MEMCFG2 = 0x8000.01c0
;--------------------------------------------------------------------------
ldr sp,=SVCStack ; Define Stacks
bl InitStacks
;--------------------------------------------------------------------------
;
; Copy the read-write data block from ROM to RAM.
;
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
LDR r0,=|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1,=|Image$$RW$$Base| ; and RAM copy
LDR r3,=|Image$$ZI$$Base|
;Zero init base => top of initialised data
CMP r0,r1 ; Check that they are different
BEQ %F1
0
CMP r1,r3 ; Copy init data
LDRCC r2,[r0],#4
STRCC r2,[r1],#4
BCC %B0
1
LDR r1,=|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2,#0
2
CMP r3,r1 ; Zero init
STRCC r2,[r3],#4
BCC %B2
;------------------------------------------------------------------
;test T1 Interrupt
ldr r12,=0x80000000
ldr r1,=0x10
str r1,[r12,#0x100]
ldr r1,=0xd0
str r1,[r12,#0x300]
ldr r0,=0x100
str r0,[r12,#0x280]
;------------------------------------------------------------------
program
ldr r12,=0x80000000
ldrb r2,[r12,#0x3]
eor r2,r2,#0x01
strb r2,[r12,#0x3]
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#USERMODE
msr cpsr,r1
;msr cpsr_cxsf,r1 ;UserMode
ldr sp,=UserStack
IMPORT C_vMain
bl C_vMain ; Call the actual C program
b ResetHandler ; Precautionary
;------------------------------------------------------------------
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr,r1
;msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr,r1
;msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr,r1
;msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr,r1
;msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr,r1
;msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack
;USER mode is not initialized.
mov pc,lr ;The LR register may be not valid for the mode changes.
;
;*****************************************************************************
;
; Zero-initialized read/write data area for stacks.
; This area is determined by the RW value in the Linker under "entry and base".
;*****************************************************************************
AREA SYS_STK, DATA, READWRITE, NOINIT
;*****************************************************************************
;
; Memory buffers to contain the stacks for the various processor modes which
; we will be using.
;
;*****************************************************************************
SVCStack_start % _SVC_STKSIZE ;0x2001800
SVCStack
UndefStack_start % _UND_STKSIZE ;0x2001C00
UndefStack
AbortStack_start % _ABT_STKSIZE ;0x2001D00
AbortStack
IRQStack_start % _IRQ_STKSIZE ;0x2001E00
IRQStack
FIQStack_start % _FIQ_STKSIZE ;0x2001F00
FIQStack ;0x2002000
UserStack_start % _USE_STKSIZE
UserStack
AREA ISR_HOOK, DATA, READWRITE, NOINIT
^ IBADDR
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;
;*****************************************************************************
;
END⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -