ep7312.h

Cirrus Logic公司的EP7312的定时器T1的使用源码

#define OVERR	0x00000400  /* UART overrun error */

#define UBRLCR1	0x04c0	/* UART Bit Rate and Line Control register --------- */
#define BRDIV	0x00000fff  /* Bit rate divisor */
#define BR_115200    1
#define BR_57600     3
#define BR_38400     5
#define BR_19200     11
#define BR_9600      23
#define BR_2400      95
#define BR_1200      191
#define BREAK	0x00001000  /* Set Tx high */
#define PRTEN	0x00002000  /* Parity enable */
#define EVENPRT 0x00004000  /* Even parity */
#define XSTOP	0x00008000  /* Extra stop bit */
#define FIFOEN  0x00010000  /* Enable FIFO */
#define WRDLEN	0x00060000  /* Word length */
#define WRDLEN_SHIFT	17
#define WL_5	    0x0	    /*   5 bits */
#define WL_6	    0x1	    /*   6 bits */
#define WL_7	    0x2	    /*   7 bits */
#define WL_8	    0x3	    /*   8 bits */

#define SYNCIO	0x0500
#define	TXFRMEN	0x00004000  /* Initiate data transfer */
#define	SMCKEN	0x00002000  /* Enable sample clock on SMPLCK */
#define FRLEN	0x00001f00  /* Frame length */
#define FRLEN_SHIFT	8
#define ADCCFB	0x000000ff  /* ADC Configuration byte */
#define ADCRSW	0x0000ffff  /* ADC result word */

#define PALLSW	0x0540	/* Least-significant 32-bit word of LCD Palette reg. */
#define PALMSW	0x0580	/* Most-significant 32-bit word of LCD Palette reg. */

#define STFCLR	0x05c0	/* Write to clear all start up reason flags -------- */
#define BLEOI	0x0600	/* Write to clear Battery Low interrupt ------------ */
#define MCEOI	0x0640	/* Write to clear Media Changed interrupt ---------- */
#define TEOI	0x0680	/* Write to clear Tick and Watchdog interrupt ------ */
#define TC1EOI	0x06c0	/* Write to clear TC1 interrupt -------------------- */
#define TC2EOI	0x0700	/* Write to clear TC2 interrupt -------------------- */
#define RTCEOI	0x0740	/* Write to clear RTC Match interrupt -------------- */
#define UMSEOI	0x0780	/* Write to clear UART Modem Status Changed interrupt*/
#define COEOI	0x07c0	/* Write to clear Codec Sound interrupt ------------ */
#define HALT	0x0800	/* Write to enter idle state ----------------------- */
#define STDBY	0x0840	/* Write to standby state -------------------------- */

#define FRBADDR	0x1000	/* LCD Frame Buffer Start Address register --------- */

#define SYSCON2	0x1100	/* System Control register 2 ----------------------- */
#define SERSEL	0x00000001  /* 0 = Master/slave SSI2, 1 = Codec */
#define KBD6	0x00000002  /* 1 = PADR[5:0] generates keyboard interrupts */
#define DRAMSZ	0x00000004  /* 0 = 32-bit DRAM, 1 = 16-bit DRAM */
#define KBWEN	0x00000008  /* enable keyboard wakeup */
#define SS2TXEN	0x00000010  /* transmit enable for SSI2 */
//#define PCMCIA1	0x00000020  /* enable CL-PS6700 for PCMCIA slot 1 */
//#define PCMCIA2	0x00000040  /* enable CL-PS6700 for PCMCIA slot 2 */
#define SS2RXEN	0x00000080  /* receive enable for SSI2 */
#define UART2EN 0x00000100  /* enable UART2 */
#define SS2MAEN	0x00000200  /* master mode enable for SSI2 */
#define OSTB	0x00001000  /* operating system timing bit, for 13MHz mode */
#define CLKENSL	0x00002000  /* select RUN/CLKEN signal: 0 = CLKEN, 1 = RUN */
#define BUZFREQ	0x00004000  /* buzzer frequency: 0 = timer, 1 = 500Hz */

#define SYSFLG2	0x1140	/* System Status Flag register 2 ------------------- */
#define SS2RXOF	0x00000001  /* SSI2 RX FIFO overflow */
#define RESVAL	0x00000002  /* SSI2 RX FIFO residual byte, cleared by popping */
#define RESFRM	0x00000004  /* SSI2 RX FIFO residual byte, cleared by frame */
#define SS2RXFE	0x00000008  /* SSI2 RX FIFO empty */
#define SS2TXFF	0x00000010  /* SSI2 TX FIFO full */
#define SS2TXUF	0x00000020  /* SSI2 TX FIFO underflow */
#define CKMODE	0x00000040  /* 0 = 18.432MHz PLL, 1 = 13MHz external clock */
#define UBUSY2	0x00000800  /* UART2 transmitter busy */
#define URXFE2	0x00400000  /* UART2 receiver FIFO empty */
#define UTXFF2	0x00800000  /* UART2 transmit FIFO full */

#define INTSR2	0x1240	/* Interrupt Status register 2 --------------------- */
#define KBDINT	0x00000001  /* keyboard interrupt */
#define SS2RX	0x00000002  /* SSI2 receive FIFO half-full interrupt */
#define SS2TX	0x00000004  /* SSI2 transmit FIFO half-empty interrupt */
#define UTXINT2	0x00001000  /* UART2 transmit FIFO half-empty interrupt */
#define URXINT2	0x00002000  /* UART2 receive FIFO half-full interrupt */

#define INTMR2	0x1280	/* Interrupt Mask register 2 ----------------------- */
#define UARTDR2	0x1480	/* UART2 Data register ----------------------------- */
#define UBRLCR2	0x14c0	/* UART2 Control register -------------------------- */
#define SS2DR	0x1500	/* Master/slave SSI2 data register ----------------- */
#define SRXEOF	0x1600	/* Write to clear RX FIFO overflow flag ------------ */
#define SS2POP	0x16c0	/* Write to pop SSI2 residual byte into RX FIFO ---- */
#define KBDEOI	0x1700	/* Write to clear keyboard interrupt --------------- */

#define DAIR	0x2000	/* DAI Control register ---------------------------- */
#define DAIDR0	0x2040	/* DAI Data register 0 ----------------------------- */
#define DAIDR1	0x2080	/* DAI Data register 1 ----------------------------- */
#define DAIDR2	0x20c0	/* DAI Data register 2 ----------------------------- */
#define DAISR	0x2100	/* DAI Status register ----------------------------- */

#define SYSCON3	0x2200	/* System Control register 3 ----------------------- */
#define ADCCON	0x00000001  /* ADC configuration */
#define CLKCTL	0x00000006  /* processor clock control */
#define CLKCTL_18      0x0  /* 18.432 MHz */
#define CLKCTL_36      0x2  /* 36.864 MHz */
#define CLKCTL_49      0x4  /* 49.152 MHz */
#define CLKCTL_73      0x6  /* 73.728 MHz */
#define DAISEL	0x00000008  /* DAI select */
#define ADCCKNSEN 0x000010  /* ADC clock sense */
#define VERSN	0x000000e0  /* additional version bits, will always read '000' on the EP7312 */
//#define VERSN_SHIFT	5
//#define FASTWAKE 0x0000100  /* Wakeup clock select: 0=8Hz, 1=4kHz */
#define ENPD67	0x00000400  /* Port D bits 6 and 7 enable. when set,as GPIO; clear,as SDQM0 and SDQM1. must be clear in order to properly use SDRAM */

#define INTSR3	0x2240	/* Interrupt Status register 3 --------------------- */
#define DAIINT	0x00000001  /* DAI interface interrupt (FIQ) */

#define INTMR3	0x2280	/* Interrupt Mask register 3 ----------------------- */
#define DAIINTMASK 0x00000001	/* DAI interface interrupt Mask */

#define LEDFLSH	0x22C0	/* LED Flash control register ---------------------- */
#define LEDFLSH_RATE       0x03  /* flash rate */
#define LEDFLSH_RATE_SHIFT 0
#define LEDFLSH_DUTY       0x3c  /* duty ratio */
#define LEDFLSH_DUTY_SHIFT 2
#define LEDFLSH_ENABLE     0x40  /* enable */

#define SDCONF	0x2300	/* SDRAM Configuration Register */
#define CASLAT	0x00000003	/* Number of clock cycles after CAS before the device is ready for reading or writing */
#define CAS_2	0x2	/* CAS latency = 2 */
#define CAS_3	0x3	/* CAS latency = 3 , default CAS latency =2 */
#define SDSIZE	0x00000060	/* Indicates the capacity of each SDRAM device */
#define SDSIZE_16	0x0	/* 16Mbir SDRAM */
#define SDSIZE_64	0x1	/* 64Mbir SDRAM */
#define SDSIZE_128	0x2	/* 128Mbir SDRAM */
#define SDSIZE_256	0x3	/* 256Mbir SDRAM */
#define SDWIDTH	0x00000180	/* The width of each SDRAM device */
#define SDRAM_4	0x0	/* 4bits SDRAM */
#define SDRAM_8	0x1	/* bits SDRAM */
#define SDRAM_16	0x2	/* 4bits SDRAM */
#define SDRAM_32	0x3	/* 4bits SDRAM */
#define SDCLKCTL	0x00000200	/* Control over the SDRAM clock */
#define SDACTIVE	0x00000400	/* Enable the SDRAM controller, 0: Disable ; 1: Enable */

#define SDRFPR	0x2340	/* SDRAM Refresh Register */
#define REFRATE	0x0000ffff	/* determin the interval between SDRAM refresh commands, 0xff as default */

#define UNIQID	0x2440	/* 32-bits unique ID for EP7312 device */


/*
 * EP7211 PCMCIA memory constants
 *
 * Need to #define PCMCIA_BASE before using these macros.

#define PCMCIA_ATTR8(a)	(PCMCIA_BASE+0x00000000+(a))
#define PCMCIA_MEM(a)	(PCMCIA_BASE+0x04000000+(a))
#define PCMCIA_IO8(a)	(PCMCIA_BASE+0x08000000+(a))
#define PCMCIA_IO16(a)	(PCMCIA_BASE+0x0c000000+((a) & ~3)+(((a) & 2) << 24))
*/

#endif