mpc8260.h

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#define ORxS_IBID	0x00000010	/* Internal Bank Interleaving Disable*/

#define ORxS_BPD_2	0x00000000	/* 2 Banks Per Device		*/
#define ORxS_BPD_4	0x00002000	/* 4 Banks Per Device		*/
#define ORxS_BPD_8	0x00004000	/* 8 Banks Per Device		*/

/* ROWST values for xSDMR[PBI] = 0 */
#define ORxS_ROWST_PBI0_A7  0x00000400	/* Row Start Address Bit is A7	*/
#define ORxS_ROWST_PBI0_A8  0x00000800	/* Row Start Address Bit is A8	*/
#define ORxS_ROWST_PBI0_A9  0x00000c00	/* Row Start Address Bit is A9	*/
#define ORxS_ROWST_PBI0_A10 0x00001000	/* Row Start Address Bit is A10	*/
#define ORxS_ROWST_PBI0_A11 0x00001400	/* Row Start Address Bit is A11	*/
#define ORxS_ROWST_PBI0_A12 0x00001800	/* Row Start Address Bit is A12	*/
#define ORxS_ROWST_PBI0_A13 0x00001c00	/* Row Start Address Bit is A13	*/

/* ROWST values for xSDMR[PBI] = 1 */
#define ORxS_ROWST_PBI1_A0  0x00000000	/* Row Start Address Bit is A0	*/
#define ORxS_ROWST_PBI1_A1  0x00000200	/* Row Start Address Bit is A1	*/
#define ORxS_ROWST_PBI1_A2  0x00000400	/* Row Start Address Bit is A2	*/
#define ORxS_ROWST_PBI1_A3  0x00000600	/* Row Start Address Bit is A3	*/
#define ORxS_ROWST_PBI1_A4  0x00000800	/* Row Start Address Bit is A4	*/
#define ORxS_ROWST_PBI1_A5  0x00000a00	/* Row Start Address Bit is A5	*/
#define ORxS_ROWST_PBI1_A6  0x00000c00	/* Row Start Address Bit is A6	*/
#define ORxS_ROWST_PBI1_A7  0x00000e00	/* Row Start Address Bit is A7	*/
#define ORxS_ROWST_PBI1_A8  0x00001000	/* Row Start Address Bit is A8	*/
#define ORxS_ROWST_PBI1_A9  0x00001200	/* Row Start Address Bit is A9	*/
#define ORxS_ROWST_PBI1_A10 0x00001400	/* Row Start Address Bit is A10	*/
#define ORxS_ROWST_PBI1_A11 0x00001600	/* Row Start Address Bit is A11	*/
#define ORxS_ROWST_PBI1_A12 0x00001800	/* Row Start Address Bit is A12	*/

#define ORxS_NUMR_9	0x00000000	/*  9 Row Address Lines		*/
#define ORxS_NUMR_10	0x00000040	/* 10 Row Address Lines		*/
#define ORxS_NUMR_11	0x00000080	/* 11 Row Address Lines		*/
#define ORxS_NUMR_12	0x000000c0	/* 12 Row Address Lines		*/
#define ORxS_NUMR_13	0x00000100	/* 13 Row Address Lines		*/
#define ORxS_NUMR_14	0x00000140	/* 14 Row Address Lines		*/
#define ORxS_NUMR_15	0x00000180	/* 15 Row Address Lines		*/
#define ORxS_NUMR_16	0x000001c0	/* 16 Row Address Lines		*/

/* helper to determine the AM for a given size (SDRAM mode) */
#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */

/*-----------------------------------------------------------------------
 * ORx - Memory Controller: Option Register - GPCM Mode			10-18
 */
#define ORxG_AM_MSK	0xffff8000	/* Address Mask Mask		*/
#define ORxG_BCTLD	0x00001000	/* Data Buffer Control Disable	*/
#define ORxG_CSNT	0x00000800	/* Chip Select Negation Time	*/
#define ORxG_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask*/
#define ORxG_SCY_MSK	0x000000f0	/* Cycle Lenght in Clocks	*/
#define ORxG_SETA	0x00000008	/* External Access Termination	*/
#define ORxG_TRLX	0x00000004	/* Timing Relaxed		*/
#define ORxG_EHTR	0x00000002	/* Extended Hold Time on Read	*/

#define ORxG_ACS_DIV1	0x00000000	/* CS is output at the same time*/
#define ORxG_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later*/
#define ORxG_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later*/

#define ORxG_SCY_0_CLK	0x00000000	/*  0 clock cycles wait states	*/
#define ORxG_SCY_1_CLK	0x00000010	/*  1 clock cycles wait states	*/
#define ORxG_SCY_2_CLK	0x00000020	/*  2 clock cycles wait states	*/
#define ORxG_SCY_3_CLK	0x00000030	/*  3 clock cycles wait states	*/
#define ORxG_SCY_4_CLK	0x00000040	/*  4 clock cycles wait states	*/
#define ORxG_SCY_5_CLK	0x00000050	/*  5 clock cycles wait states	*/
#define ORxG_SCY_6_CLK	0x00000060	/*  6 clock cycles wait states	*/
#define ORxG_SCY_7_CLK	0x00000070	/*  7 clock cycles wait states	*/
#define ORxG_SCY_8_CLK	0x00000080	/*  8 clock cycles wait states	*/
#define ORxG_SCY_9_CLK	0x00000090	/*  9 clock cycles wait states	*/
#define ORxG_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states	*/
#define ORxG_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states	*/
#define ORxG_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states	*/
#define ORxG_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states	*/
#define ORxG_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states	*/
#define ORxG_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states	*/

/*-----------------------------------------------------------------------
 * ORx - Memory Controller: Option Register - UPM Mode			10-20
 */
#define ORxU_AM_MSK	0xffff8000	/* Address Mask Mask		*/
#define ORxU_BCTLD	0x00001000	/* Data Buffer Control Disable	*/
#define ORxU_BI		0x00000100	/* Burst Inhibit		*/
#define ORxU_EHTR_MSK	0x00000006	/* Extended Hold Time on Read Mask*/

#define ORxU_EHTR_NORM	0x00000000	/* Normal Timing		*/
#define ORxU_EHTR_1IDLE	0x00000002	/* One Idle Clock Cycle Inserted*/
#define ORxU_EHTR_4IDLE	0x00000004	/* Four Idle Clock Cycles Inserted*/
#define ORxU_EHTR_8IDLE	0x00000006	/* Eight Idle Clock Cycles Inserted*/


/* helpers to convert values into an OR address mask (GPCM mode) */
#define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
#define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)


/*-----------------------------------------------------------------------
 * PSDMR - 60x SDRAM Mode Register					10-21
 */
#define PSDMR_PBI	     0x80000000	/* Page-based Interleaving	*/
#define PSDMR_RFEN	     0x40000000	/* Refresh Enable		*/
#define PSDMR_OP_MSK	     0x38000000	/* SDRAM Operation Mask		*/
#define PSDMR_SDAM_MSK	     0x07000000	/* SDRAM Address Multiplex Mask	*/
#define PSDMR_BSMA_MSK	     0x00e00000	/* Bank Select Muxd Addr Line Mask*/
#define PSDMR_SDA10_MSK	     0x001c0000	/* A10 Control Mask		*/
#define PSDMR_RFRC_MSK	     0x00038000	/* Refresh Recovery Mask	*/
#define PSDMR_PRETOACT_MSK   0x00007000	/* Precharge to Activate Intvl Mask*/
#define PSDMR_ACTTORW_MSK    0x00000e00	/* Activate to Read/Write Intvl Mask*/
#define PSDMR_BL	     0x00000100	/* Burst Length			*/
#define PSDMR_LDOTOPRE_MSK   0x000000c0	/* Last Data Out to Precharge Mask*/
#define PSDMR_WRC_MSK	     0x00000030	/* Write Recovery Time Mask	*/
#define PSDMR_EAMUX	     0x00000008	/* External Address Multiplexing*/
#define PSDMR_BUFCMD	     0x00000004	/* SDRAM ctl lines asrtd for 2 cycles*/
#define PSDMR_CL_MSK	     0x00000003	/* CAS Latency Mask		*/

#define PSDMR_OP_NORM	     0x00000000	/* Normal Operation		*/
#define PSDMR_OP_CBRR	     0x08000000	/* CBR Refresh			*/
#define PSDMR_OP_SELFR	     0x10000000	/* Self Refresh			*/
#define PSDMR_OP_MRW	     0x18000000	/* Mode Register Write		*/
#define PSDMR_OP_PREB	     0x20000000	/* Precharge Bank		*/
#define PSDMR_OP_PREA	     0x28000000	/* Precharge All Banks		*/
#define PSDMR_OP_ACTB	     0x30000000	/* Activate Bank		*/
#define PSDMR_OP_RW	     0x38000000	/* Read/Write			*/

#define PSDMR_SDAM_A13_IS_A5 0x00000000	/* SDRAM Address Multiplex A13 is A5 */
#define PSDMR_SDAM_A14_IS_A5 0x01000000	/* SDRAM Address Multiplex A14 is A5 */
#define PSDMR_SDAM_A15_IS_A5 0x02000000	/* SDRAM Address Multiplex A15 is A5 */
#define PSDMR_SDAM_A16_IS_A5 0x03000000	/* SDRAM Address Multiplex A16 is A5 */
#define PSDMR_SDAM_A17_IS_A5 0x04000000	/* SDRAM Address Multiplex A17 is A5 */
#define PSDMR_SDAM_A18_IS_A5 0x05000000	/* SDRAM Address Multiplex A18 is A5 */

#define PSDMR_BSMA_A12_A14   0x00000000	/* A12 - A14			*/
#define PSDMR_BSMA_A13_A15   0x00200000	/* A13 - A15			*/
#define PSDMR_BSMA_A14_A16   0x00400000	/* A14 - A16			*/
#define PSDMR_BSMA_A15_A17   0x00600000	/* A15 - A17			*/
#define PSDMR_BSMA_A16_A18   0x00800000	/* A16 - A18			*/
#define PSDMR_BSMA_A17_A19   0x00a00000	/* A17 - A19			*/
#define PSDMR_BSMA_A18_A20   0x00c00000	/* A18 - A20			*/
#define PSDMR_BSMA_A19_A21   0x00e00000	/* A19 - A21			*/

/* SDA10 values for xSDMR[PBI] = 0 */
#define PSDMR_SDA10_PBI0_A12 0x00000000	/* "A10" Control is A12		*/
#define PSDMR_SDA10_PBI0_A11 0x00040000	/* "A10" Control is A11		*/
#define PSDMR_SDA10_PBI0_A10 0x00080000	/* "A10" Control is A10		*/
#define PSDMR_SDA10_PBI0_A9  0x000c0000	/* "A10" Control is A9		*/
#define PSDMR_SDA10_PBI0_A8  0x00100000	/* "A10" Control is A8		*/
#define PSDMR_SDA10_PBI0_A7  0x00140000	/* "A10" Control is A7		*/
#define PSDMR_SDA10_PBI0_A6  0x00180000	/* "A10" Control is A6		*/
#define PSDMR_SDA10_PBI0_A5  0x001c0000	/* "A10" Control is A5		*/

/* SDA10 values for xSDMR[PBI] = 1 */
#define PSDMR_SDA10_PBI1_A10 0x00000000	/* "A10" Control is A10		*/
#define PSDMR_SDA10_PBI1_A9  0x00040000	/* "A10" Control is A9		*/
#define PSDMR_SDA10_PBI1_A8  0x00080000	/* "A10" Control is A8		*/
#define PSDMR_SDA10_PBI1_A7  0x000c0000	/* "A10" Control is A7		*/
#define PSDMR_SDA10_PBI1_A6  0x00100000	/* "A10" Control is A6		*/
#define PSDMR_SDA10_PBI1_A5  0x00140000	/* "A10" Control is A5		*/
#define PSDMR_SDA10_PBI1_A4  0x00180000	/* "A10" Control is A4		*/
#define PSDMR_SDA10_PBI1_A3  0x001c0000	/* "A10" Control is A3		*/

#define PSDMR_RFRC_3_CLK     0x00008000	/*  3 Clocks			*/
#define PSDMR_RFRC_4_CLK     0x00010000	/*  4 Clocks			*/
#define PSDMR_RFRC_5_CLK     0x00018000	/*  5 Clocks			*/
#define PSDMR_RFRC_6_CLK     0x00020000	/*  6 Clocks			*/
#define PSDMR_RFRC_7_CLK     0x00028000	/*  7 Clocks			*/
#define PSDMR_RFRC_8_CLK     0x00030000	/*  8 Clocks			*/
#define PSDMR_RFRC_16_CLK    0x00038000	/* 16 Clocks			*/

#define PSDMR_PRETOACT_8W    0x00000000	/* 8 Clock-cycle Wait States	*/
#define PSDMR_PRETOACT_1W    0x00001000	/* 1 Clock-cycle Wait States	*/
#define PSDMR_PRETOACT_2W    0x00002000	/* 2 Clock-cycle Wait States	*/
#define PSDMR_PRETOACT_3W    0x00003000	/* 3 Clock-cycle Wait States	*/
#define PSDMR_PRETOACT_4W    0x00004000	/* 4 Clock-cycle Wait States	*/
#define PSDMR_PRETOACT_5W    0x00005000	/* 5 Clock-cycle Wait States	*/
#define PSDMR_PRETOACT_6W    0x00006000	/* 6 Clock-cycle Wait States	*/
#define PSDMR_PRETOACT_7W    0x00007000	/* 7 Clock-cycle Wait States	*/

#define PSDMR_ACTTORW_8W     0x00000000	/* 8 Clock-cycle Wait States	*/
#define PSDMR_ACTTORW_1W     0x00000200	/* 1 Clock-cycle Wait States	*/
#define PSDMR_ACTTORW_2W     0x00000400	/* 2 Clock-cycle Wait States	*/
#define PSDMR_ACTTORW_3W     0x00000600	/* 3 Clock-cycle Wait States	*/
#define PSDMR_ACTTORW_4W     0x00000800	/* 4 Clock-cycle Wait States	*/
#define PSDMR_ACTTORW_5W     0x00000a00	/* 5 Clock-cycle Wait States	*/
#define PSDMR_ACTTORW_6W     0x00000c00	/* 6 Clock-cycle Wait States	*/
#define PSDMR_ACTTORW_7W     0x00000e00	/* 7 Clock-cycle Wait States	*/

#define PSDMR_LDOTOPRE_0C    0x00000000	/* 0 Clock Cycles		*/
#define PSDMR_LDOTOPRE_1C    0x00000040	/* 1 Clock Cycles		*/
#define PSDMR_LDOTOPRE_2C    0x00000080	/* 2 Clock Cycles		*/

#define PSDMR_WRC_4C	     0x00000000	/* 4 Clock Cycles		*/
#define PSDMR_WRC_1C	     0x00000010	/* 1 Clock Cycles		*/
#define PSDMR_WRC_2C	     0x00000020	/* 2 Clock Cycles		*/
#define PSDMR_WRC_3C	     0x00000030	/* 3 Clock Cycles		*/

#define PSDMR_CL_1	     0x00000001	/* CAS Latency = 1		*/
#define PSDMR_CL_2	     0x00000002	/* CAS Latency = 2		*/
#define PSDMR_CL_3	     0x00000003	/* CAS Latency = 3		*/

/*-----------------------------------------------------------------------
 * LSDMR - Local Bus SDRAM Mode Register			 	10-24
 */

/*
 * No definitions here - the LSDMR has the same fields as the PSDMR.
 */

/*-----------------------------------------------------------------------
 * MPTPR - Memory Refresh Timer Prescaler Register			10-32
 * See User's Manual Errata for the changed definition (matches the
 * 8xx now).  The wrong prescaler definition causes excessive refreshes
 * (typically "divide by 2" when "divide by 32" is intended) which will
 * cause unnecessary memory subsystem slowdown.
 */
#define MPTPR_PTP_MSK	0xff00		/* Periodic Timers Prescaler Mask */
#define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2		*/
#define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4		*/
#define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8		*/
#define MPTPR_PTP_DIV16	0x0400		/* BRGCLK divided by 16		*/
#define MPTPR_PTP_DIV32	0x0200		/* BRGCLK divided by 32		*/
#define MPTPR_PTP_DIV64	0x0100		/* BRGCLK divided by 64		*/


/*-----------------------------------------------------------------------
 * TGCR1/TGCR2 - Timer Global Configuration Registers			17-4
 */
#define TGCR1_CAS2	0x80		/* Cascade Timer 1 and 2	*/
#define TGCR1_STP2	0x20		/* Stop timer   2		*/
#define TGCR1_RST2	0x10		/* Reset timer  2		*/
#define TGCR1_GM1	0x08		/* Gate Mode for Pin 1		*/
#define TGCR1_STP1	0x02		/* Stop timer   1		*/