mpc8260.h

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/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8260.h
 *
 * MPC8255 / MPC8260 specific definitions
 */

#ifndef __MPC8260_H__
#define __MPC8260_H__

#ifdef CONFIG_MPC8255
#define CPU_ID_STR	"MPC8255"
#endif
#ifndef CPU_ID_STR
#if defined(CONFIG_MPC8272_FAMILY)
#define CPU_ID_STR	"MPC8272"
#else
#define CPU_ID_STR	"MPC8260"
#endif
#endif /* !CPU_ID_STR */

/*-----------------------------------------------------------------------
 * Exception offsets (PowerPC standard)
 */
#define EXC_OFF_SYS_RESET	0x0100	/* System reset			*/


/*-----------------------------------------------------------------------
 * BCR - Bus Configuration Register					 4-25
 */
#define BCR_EBM		0x80000000	/* External Bus Mode		*/
#define BCR_APD_MSK	0x70000000	/* Address Phase Delay Mask	*/
#define BCR_L2C		0x08000000	/* Secondary Cache Controller	*/
#define BCR_L2D_MSK	0x07000000	/* L2 Cache Hit Delay Mask	*/
#define BCR_PLDP	0x00800000	/* Pipeline Maximum Depth	*/
#define BCR_EAV		0x00400000	/* Enable Address Visibility	*/
#define BCR_ETM		0x00080000	/* Compatibility Mode Enable	*/
#define BCR_LETM	0x00040000	/* LocalBus Compatibility Mode Enable*/
#define BCR_EPAR	0x00020000	/* Even Parity			*/
#define BCR_LEPAR	0x00010000	/* Local Bus Even Parity	*/
#define BCR_NPQM0	0x00008000	/* Non PowerQUICC-II Master 0	*/
#define BCR_NPQM1	0x00004000	/* Non PowerQUICC-II Master 1	*/
#define BCR_NPQM2	0x00002000	/* Non PowerQUICC-II Master 2	*/
#define BCR_EXDD	0x00000400	/* External Master Delay Disable*/
#define BCR_ISPS	0x00000010	/* Internal Space Port Size	*/

/*-----------------------------------------------------------------------
 * PPC_ACR - 60x Bus Arbiter Configuration Register			 4-28
 */
#define PPC_ACR_DBGD	0x20		/* Data Bus Grant Delay		*/
#define PPC_ACR_EARB	0x10		/* External Arbitration		*/
#define PPC_ACR_PRKM_MSK 0x0f		/* Parking Master		*/

#define PPC_ACR_PRKM_CPMH 0x00		/* CPM high request level	*/
#define PPC_ACR_PRKM_CPMM 0x01		/* CPM middle request level	*/
#define PPC_ACR_PRKM_CPML 0x02		/* CPM low request level	*/
#define PPC_ACR_PRKM_CORE 0x06		/* Internal Core		*/
#define PPC_ACR_PRKM_EXT1 0x07		/* External Master 1		*/
#define PPC_ACR_PRKM_EXT2 0x08		/* External Master 2		*/
#define PPC_ACR_PRKM_EXT3 0x09		/* External Master 3		*/

/*-----------------------------------------------------------------------
 * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers		 4-28
 */
#define PPC_ALRH_PF0_MSK  0xf0000000	/* Priority Field  0 Mask	*/
#define PPC_ALRH_PF1_MSK  0x0f000000	/* Priority Field  1 Mask	*/
#define PPC_ALRH_PF2_MSK  0x00f00000	/* Priority Field  2 Mask	*/
#define PPC_ALRH_PF3_MSK  0x000f0000	/* Priority Field  3 Mask	*/
#define PPC_ALRH_PF4_MSK  0x0000f000	/* Priority Field  4 Mask	*/
#define PPC_ALRH_PF5_MSK  0x00000f00	/* Priority Field  5 Mask	*/
#define PPC_ALRH_PF6_MSK  0x000000f0	/* Priority Field  6 Mask	*/
#define PPC_ALRH_PF7_MSK  0x0000000f	/* Priority Field  7 Mask	*/
#define PPC_ALRL_PF8_MSK  0xf0000000	/* Priority Field  8 Mask	*/
#define PPC_ALRL_PF9_MSK  0x0f000000	/* Priority Field  9 Mask	*/
#define PPC_ALRL_PF10_MSK 0x00f00000	/* Priority Field 10 Mask	*/
#define PPC_ALRL_PF11_MSK 0x000f0000	/* Priority Field 11 Mask	*/
#define PPC_ALRL_PF12_MSK 0x0000f000	/* Priority Field 12 Mask	*/
#define PPC_ALRL_PF13_MSK 0x00000f00	/* Priority Field 13 Mask	*/
#define PPC_ALRL_PF14_MSK 0x000000f0	/* Priority Field 14 Mask	*/
#define PPC_ALRL_PF15_MSK 0x0000000f	/* Priority Field 15 Mask	*/

/*-----------------------------------------------------------------------
 * LCL_ACR - Local Bus Arbiter Configuration Register			 4-29
 */
#define LCL_ACR_DBGD	0x20		/* Data Bus Grant Delay		*/
#define LCL_ACR_PRKM_MSK 0x0f		/* Parking Master		*/

#define LCL_ACR_PRKM_CPMH 0x00		/* CPM high request level	*/
#define LCL_ACR_PRKM_CPMM 0x01		/* CPM middle request level	*/
#define LCL_ACR_PRKM_CPML 0x02		/* CPM low request level	*/
#define LCL_ACR_PRKM_HOST 0x03		/* Host Bridge			*/

/*-----------------------------------------------------------------------
 * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers		 4-30
 */
#define LCL_ALRH_PF0_MSK  0xf0000000	/* Priority Field  0 Mask	*/
#define LCL_ALRH_PF1_MSK  0x0f000000	/* Priority Field  1 Mask	*/
#define LCL_ALRH_PF2_MSK  0x00f00000	/* Priority Field  2 Mask	*/
#define LCL_ALRH_PF3_MSK  0x000f0000	/* Priority Field  3 Mask	*/
#define LCL_ALRH_PF4_MSK  0x0000f000	/* Priority Field  4 Mask	*/
#define LCL_ALRH_PF5_MSK  0x00000f00	/* Priority Field  5 Mask	*/
#define LCL_ALRH_PF6_MSK  0x000000f0	/* Priority Field  6 Mask	*/
#define LCL_ALRH_PF7_MSK  0x0000000f	/* Priority Field  7 Mask	*/
#define LCL_ALRL_PF8_MSK  0xf0000000	/* Priority Field  8 Mask	*/
#define LCL_ALRL_PF9_MSK  0x0f000000	/* Priority Field  9 Mask	*/
#define LCL_ALRL_PF10_MSK 0x00f00000	/* Priority Field 10 Mask	*/
#define LCL_ALRL_PF11_MSK 0x000f0000	/* Priority Field 11 Mask	*/
#define LCL_ALRL_PF12_MSK 0x0000f000	/* Priority Field 12 Mask	*/
#define LCL_ALRL_PF13_MSK 0x00000f00	/* Priority Field 13 Mask	*/
#define LCL_ALRL_PF14_MSK 0x000000f0	/* Priority Field 14 Mask	*/
#define LCL_ALRL_PF15_MSK 0x0000000f	/* Priority Field 15 Mask	*/

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration Register				 4-31
 */
#define SIUMCR_BBD	0x80000000	/* Bus Busy Disable		*/
#define SIUMCR_ESE	0x40000000	/* External Snoop Enable	*/
#define SIUMCR_PBSE	0x20000000	/* Parity Byte Select Enable	*/
#define SIUMCR_CDIS	0x10000000	/* Core Disable			*/
#define SIUMCR_DPPC00	0x00000000	/* Data Parity Pins Configuration*/
#define SIUMCR_DPPC01	0x04000000	/* - " -			*/
#define SIUMCR_DPPC10	0x08000000	/* - " -			*/
#define SIUMCR_DPPC11	0x0c000000	/* - " -			*/
#define SIUMCR_L2CPC00	0x00000000	/* L2 Cache Pins Configuration	*/
#define SIUMCR_L2CPC01	0x01000000	/* - " -			*/
#define SIUMCR_L2CPC10	0x02000000	/* - " -			*/
#define SIUMCR_L2CPC11	0x03000000	/* - " -			*/
#define SIUMCR_LBPC00	0x00000000	/* Local Bus Pins Configuration	*/
#define SIUMCR_LBPC01	0x00400000	/* - " -			*/
#define SIUMCR_LBPC10	0x00800000	/* - " -			*/
#define SIUMCR_LBPC11	0x00c00000	/* - " -			*/
#define SIUMCR_APPC00	0x00000000	/* Address Parity Pins Configuration*/
#define SIUMCR_APPC01	0x00100000	/* - " -			*/
#define SIUMCR_APPC10	0x00200000	/* - " -			*/
#define SIUMCR_APPC11	0x00300000	/* - " -			*/
#define SIUMCR_CS10PC00	0x00000000	/* CS10 Pin Configuration	*/
#define SIUMCR_CS10PC01	0x00040000	/* - " -			*/
#define SIUMCR_CS10PC10	0x00080000	/* - " -			*/
#define SIUMCR_CS10PC11	0x000c0000	/* - " -			*/
#define SIUMCR_BCTLC00	0x00000000	/* Buffer Control Configuration	*/
#define SIUMCR_BCTLC01	0x00010000	/* - " -			*/
#define SIUMCR_BCTLC10	0x00020000	/* - " -			*/
#define SIUMCR_BCTLC11	0x00030000	/* - " -			*/
#define SIUMCR_MMR00	0x00000000	/* Mask Masters Requests	*/
#define SIUMCR_MMR01	0x00004000	/* - " -			*/
#define SIUMCR_MMR10	0x00008000	/* - " -			*/
#define SIUMCR_MMR11	0x0000c000	/* - " -			*/
#define SIUMCR_LPBSE	0x00002000	/* LocalBus Parity Byte Select Enable*/

/*-----------------------------------------------------------------------
 * IMMR - Internal Memory Map Register					 4-34
 */
#define IMMR_ISB_MSK	 0xfffe0000	/* Internal Space base		*/
#define IMMR_PARTNUM_MSK 0x0000ff00	/* Part number			*/
#define IMMR_MASKNUM_MSK 0x000000ff	/* Mask number			*/

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control Register				 4-35
 */
#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count*/
#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing		*/
#define SYPCR_PBME	0x00000080	/* 60x Bus Monitor Enable	*/
#define SYPCR_LBME	0x00000040	/* Local Bus Monitor Enable	*/
#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable	*/
#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select*/
#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale	*/

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control Register			 4-40
 */
#define TMCNTSC_SEC	0x0080		/* Once Per Second Interrupt	*/
#define TMCNTSC_ALR	0x0040		/* Alarm Interrupt		*/
#define TMCNTSC_SIE	0x0008		/* Second Interrupt Enable	*/
#define TMCNTSC_ALE	0x0004		/* Alarm Interrupt Enable	*/
#define TMCNTSC_TCF	0x0002		/* Time Counter Frequency	*/
#define TMCNTSC_TCE	0x0001		/* Time Counter Enable		*/

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control Register		 4-42
 */
#if 0	/* already defined in asm/immap_8260.h */
#define PISCR_PS	0x0080		/* Periodic Interrupt Status	*/
#define PISCR_PIE	0x0004		/* Periodic Interrupt Enable	*/
#define PISCR_PTF	0x0002		/* Periodic Timer Frequency	*/
#define PISCR_PTE	0x0001		/* Periodic Timer Enable	*/
#endif

/*-----------------------------------------------------------------------
 * RSR - Reset Status Register						 5-4
 */
#define RSR_JTRS	0x00000020	/* JTAG Reset Status		*/
#define RSR_CSRS	0x00000010	/* Check Stop Reset Status	*/
#define RSR_SWRS	0x00000008	/* Software Watchdog Reset Status*/
#define RSR_BMRS	0x00000004	/* Bus Monitor Reset Status	*/
#define RSR_ESRS	0x00000002	/* External Soft Reset Status	*/
#define RSR_EHRS	0x00000001	/* External Hard Reset Status	*/

#define RSR_ALLBITS	(RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS)

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register						 5-5
 */
#define RMR_CSRE	0x00000001	/* Checkstop Reset Enable	*/

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Word					 5-8
 */