commproc.h

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#define	PROFF_ENET	PROFF_SCC1
#define	CPM_CR_ENET	CPM_CR_CH_SCC1

#define PA_ENET_RXD	((ushort)0x0001)
#define PA_ENET_TXD	((ushort)0x0002)
#define PA_ENET_TCLK	((ushort)0x0100)
#define PA_ENET_RCLK	((ushort)0x0200)

#define PB_ENET_TENA	((uint)0x00001000)

#define PC_ENET_CLSN	((ushort)0x0010)
#define PC_ENET_RENA	((ushort)0x0020)

#define SICR_ENET_MASK	((uint)0x000000ff)
#define SICR_ENET_CLKRT	((uint)0x0000002c)

#endif	/* CONFIG_SCC1_ETHERNET */

/*
 * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
 * with ethernet on FEC.
 */

#ifdef CONFIG_FEC_ENET
#define	FEC_ENET	/* Use FEC for Ethernet */
#endif	/* CONFIG_FEC_ENET */

#endif	/* CONFIG_FADS && CONFIG_MPC86x */

/***  FPS850L, FPS860L  ************************************************/

#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC2 use.
 */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */

#define PC_ENET_TENA	((ushort)0x0002)	/* PC 14 */
#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */

/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00002600)
#endif	/* CONFIG_FPS850L, CONFIG_FPS860L */

/*** GEN860T **********************************************************/
#if defined(CONFIG_GEN860T)
#undef	SCC_ENET
#define	FEC_ENET

#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 	*/
#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 	*/
#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 	*/
#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 	*/
#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 	*/
#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 	*/
#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 	*/
#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 	*/
#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 	*/
#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 	*/
#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 	*/
#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 	*/
#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 	*/
#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3-15	*/
#endif	/* CONFIG_GEN860T */

/***  GENIETV  ********************************************************/

#if defined(CONFIG_GENIETV)
/* Ethernet is only on SCC2 */

#define CONFIG_SCC2_ENET
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define CPMVEC_ENET	CPMVEC_SCC2

#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */

#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */

#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */

#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00002e00)

#endif	/* CONFIG_GENIETV */

/*** GTH ******************************************************/

#ifdef CONFIG_GTH
#ifdef CONFIG_FEC_ENET
#define	FEC_ENET	/* use FEC for EThernet */
#endif	/* CONFIG_FEC_ETHERNET */

/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
#define	PROFF_ENET	PROFF_SCC1
#define	CPM_CR_ENET	CPM_CR_CH_SCC1
#define	SCC_ENET	0

#define PA_ENET_RXD	((ushort)0x0001) /* PA15 */
#define PA_ENET_TXD	((ushort)0x0002) /* PA14 */
#define PA_ENET_TCLK	((ushort)0x0800) /* PA4 */
#define PA_ENET_RCLK	((ushort)0x0400) /* PA5 */

#define PB_ENET_TENA	((uint)0x00001000) /* PB19 */

#define PC_ENET_CLSN	((ushort)0x0010) /* PC11 */
#define PC_ENET_RENA	((ushort)0x0020) /* PC10 */

/* NOTE. This is reset for 10Mbit port only */
#define PC_ENET_RESET	((ushort)0x0100)	/* PC 7 */

#define SICR_ENET_MASK	((uint)0x000000ff)

/* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
#define SICR_ENET_CLKRT	((uint)0x00000037)

#endif	/* CONFIG_GTH */

/*** HERMES-PRO ******************************************************/

/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */

#ifdef CONFIG_HERMES

#define	FEC_ENET	/* use FEC for EThernet */
#undef	SCC_ENET


#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */

#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */

#endif	/* CONFIG_HERMES */

/***  IAD210  **********************************************************/

/* The IAD210 uses the FEC on a MPC860P for Ethernet */

#if defined(CONFIG_IAD210)

# define  FEC_ENET    /* use FEC for Ethernet */
# undef   SCC_ENET

# define PD_MII_TXD1    ((ushort) 0x1000 )	/* PD  3 */
# define PD_MII_TXD2    ((ushort) 0x0800 )	/* PD  4 */
# define PD_MII_TXD3    ((ushort) 0x0400 )	/* PD  5 */
# define PD_MII_RX_DV   ((ushort) 0x0200 )	/* PD  6 */
# define PD_MII_RX_ERR  ((ushort) 0x0100 )	/* PD  7 */
# define PD_MII_RX_CLK  ((ushort) 0x0080 )	/* PD  8 */
# define PD_MII_TXD0    ((ushort) 0x0040 )	/* PD  9 */
# define PD_MII_RXD0    ((ushort) 0x0020 )	/* PD 10 */
# define PD_MII_TX_ERR  ((ushort) 0x0010 )	/* PD 11 */
# define PD_MII_MDC     ((ushort) 0x0008 )	/* PD 12 */
# define PD_MII_RXD1    ((ushort) 0x0004 )	/* PD 13 */
# define PD_MII_RXD2    ((ushort) 0x0002 )	/* PD 14 */
# define PD_MII_RXD3    ((ushort) 0x0001 )	/* PD 15 */

# define PD_MII_MASK    ((ushort) 0x1FFF )   /* PD 3...15 */

#endif	/* CONFIG_IAD210 */

/*** ICU862  **********************************************************/

#if defined(CONFIG_ICU862)

#ifdef CONFIG_FEC_ENET
#define FEC_ENET	/* use FEC for EThernet */
#endif  /* CONFIG_FEC_ETHERNET */

#endif /* CONFIG_ICU862 */

/***  IP860  **********************************************************/

#if defined(CONFIG_IP860)
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC1 use.
 */
#define	PROFF_ENET	PROFF_SCC1
#define	CPM_CR_ENET	CPM_CR_CH_SCC1
#define	SCC_ENET	0
#define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
#define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
#define PA_ENET_TCLK	((ushort)0x0100)	/* PA  7 */

#define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
#define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
#define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */

#define PB_ENET_RESET	(uint)0x00000008	/* PB 28 */
#define PB_ENET_JABD	(uint)0x00000004	/* PB 29 */

/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
 * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 */
#define SICR_ENET_MASK	((uint)0x000000ff)
#define SICR_ENET_CLKRT	((uint)0x0000002C)
#endif	/* CONFIG_IP860 */

/*** IVMS8  **********************************************************/

/* The IVMS8 uses the FEC on a MPC860T for Ethernet */

#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)

#define	FEC_ENET	/* use FEC for EThernet */
#undef	SCC_ENET

#define	PB_ENET_POWER	((uint)0x00010000)	/* PB 15 */

#define PC_ENET_RESET	((ushort)0x0010)	/* PC 11 */

#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */

#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */

#endif	/* CONFIG_IVMS8, CONFIG_IVML24 */

/***  KUP4K, KUP4X ****************************************************/
/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */

#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)

#define	FEC_ENET	/* use FEC for EThernet */
#undef	SCC_ENET

#define	PB_ENET_POWER	((uint)0x00010000)	/* PB 15 */

#define PC_ENET_RESET	((ushort)0x0010)	/* PC 11 */

#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */

#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */

#endif	/* CONFIG_KUP4K */


/***  LANTEC  *********************************************************/

#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC2 use.
 */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */

#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */

#define PC_ENET_LBK	((ushort)0x0010)	/* PC 11 */
#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000FF00)
#define SICR_ENET_CLKRT	((uint)0x00002E00)
#endif	/* CONFIG_LANTEC v2 */

/***  LWMON  **********************************************************/

#if defined(CONFIG_LWMON)
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC2 use.
 */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0800)	/* PA  4 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */

#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */

#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00003E00)
#endif	/* CONFIG_LWMON */

/***  NX823  ***********************************************/

#if defined(CONFIG_NX823)
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC1 use.
 */
#define PROFF_ENET	PROFF_SCC2
#define CPM_CR_ENET	CPM_CR_CH_SCC2
#define SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)  /* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)  /* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0200)  /* PA  6 */
#define PA_ENET_TCLK	((ushort)0x0800)  /* PA  4 */

#define PB_ENET_TENA	((uint)0x00002000)   /* PB 18 */

#define PC_ENET_CLSN	((ushort)0x0040)  /* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)  /* PC  8 */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.