ppc440.h

F:worksip2440a board可启动u-boot-like.tar.gz F:worksip2440a board可启动u-boot-like.tar.gz

#define UIC_RSVD27	0x00000010	/* Reserved			    */
#define UIC_RSVD28	0x00000008	/* Reserved			    */
#define UIC_RSVD29	0x00000004	/* Reserved			    */
#define UIC_RSVD30	0x00000002	/* Reserved			    */
#define UIC_RSVD31	0x00000001	/* Reserved			    */
#endif	/* CONFIG_440_GX */

/*---------------------------------------------------------------------------+
|  Universal interrupt controller Base 0 interrupts (UICB0)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440_GX)
#define UICB0_UIC0CI	0x80000000	/* UIC0 Critical Interrupt	    */
#define UICB0_UIC0NCI	0x40000000	/* UIC0 Noncritical Interrupt	    */
#define UICB0_UIC1CI	0x20000000	/* UIC1 Critical Interrupt	    */
#define UICB0_UIC1NCI	0x10000000	/* UIC1 Noncritical Interrupt	    */
#define UICB0_UIC2CI	0x08000000	/* UIC2 Critical Interrupt	    */
#define UICB0_UIC2NCI	0x04000000	/* UIC2 Noncritical Interrupt	    */

#define UICB0_ALL		(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
						 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
#endif /* CONFIG_440_GX */

/*-----------------------------------------------------------------------------+
|  External Bus Controller Bit Settings
+-----------------------------------------------------------------------------*/
#define EBC_CFGADDR_MASK                0x0000003F

#define EBC_BXCR_BAS_ENCODE(n) 	((((unsigned long)(n))&0xFFF00000)<<0)
#define EBC_BXCR_BS_MASK  		0x000E0000
#define EBC_BXCR_BS_1MB   		0x00000000
#define EBC_BXCR_BS_2MB   		0x00020000
#define EBC_BXCR_BS_4MB   		0x00040000
#define EBC_BXCR_BS_8MB   		0x00060000
#define EBC_BXCR_BS_16MB  		0x00080000
#define EBC_BXCR_BS_32MB  		0x000A0000
#define EBC_BXCR_BS_64MB  		0x000C0000
#define EBC_BXCR_BS_128MB 		0x000E0000
#define EBC_BXCR_BU_MASK  		0x00018000
#define EBC_BXCR_BU_R     		0x00008000
#define EBC_BXCR_BU_W     		0x00010000
#define EBC_BXCR_BU_RW    		0x00018000
#define EBC_BXCR_BW_MASK  		0x00006000
#define EBC_BXCR_BW_8BIT  		0x00000000
#define EBC_BXCR_BW_16BIT 		0x00002000

#define EBC_BXAP_BME_ENABLED   	0x80000000
#define EBC_BXAP_BME_DISABLED  	0x00000000
#define EBC_BXAP_TWT_ENCODE(n)  	((((unsigned long)(n))&0xFF)<<23)
#define EBC_BXAP_BCE_DISABLE           0x00000000
#define EBC_BXAP_BCE_ENABLE            0x00400000
#define EBC_BXAP_CSN_ENCODE(n)  	((((unsigned long)(n))&0x3)<<18)
#define EBC_BXAP_OEN_ENCODE(n)  	((((unsigned long)(n))&0x3)<<16)
#define EBC_BXAP_WBN_ENCODE(n)  	((((unsigned long)(n))&0x3)<<14)
#define EBC_BXAP_WBF_ENCODE(n)  	((((unsigned long)(n))&0x3)<<12)
#define EBC_BXAP_TH_ENCODE(n)   	((((unsigned long)(n))&0x7)<<9)
#define EBC_BXAP_RE_ENABLED    	0x00000100
#define EBC_BXAP_RE_DISABLED   	0x00000000
#define EBC_BXAP_SOR_DELAYED   	0x00000000
#define EBC_BXAP_SOR_NONDELAYED  	0x00000080
#define EBC_BXAP_BEM_WRITEONLY 	0x00000000
#define EBC_BXAP_BEM_RW                0x00000040
#define EBC_BXAP_PEN_DISABLED  	0x00000000

#define EBC_CFG_LE_MASK      		0x80000000
#define EBC_CFG_LE_UNLOCK    		0x00000000
#define EBC_CFG_LE_LOCK    		0x80000000
#define EBC_CFG_PTD_MASK       	0x40000000
#define EBC_CFG_PTD_ENABLE     	0x00000000
#define EBC_CFG_PTD_DISABLE    	0x40000000
#define EBC_CFG_RTC_MASK               0x38000000
#define EBC_CFG_RTC_16PERCLK   	0x00000000
#define EBC_CFG_RTC_32PERCLK           0x08000000
#define EBC_CFG_RTC_64PERCLK           0x10000000
#define EBC_CFG_RTC_128PERCLK          0x18000000
#define EBC_CFG_RTC_256PERCLK          0x20000000
#define EBC_CFG_RTC_512PERCLK          0x28000000
#define EBC_CFG_RTC_1024PERCLK         0x30000000
#define EBC_CFG_RTC_2048PERCLK         0x38000000
#define EBC_CFG_ATC_MASK               0x04000000
#define EBC_CFG_ATC_HI                 0x00000000
#define EBC_CFG_ATC_PREVIOUS           0x04000000
#define EBC_CFG_DTC_MASK               0x02000000
#define EBC_CFG_DTC_HI                 0x00000000
#define EBC_CFG_DTC_PREVIOUS           0x02000000
#define EBC_CFG_CTC_MASK               0x01000000
#define EBC_CFG_CTC_HI                 0x00000000
#define EBC_CFG_CTC_PREVIOUS           0x01000000
#define EBC_CFG_OEO_MASK               0x00800000
#define EBC_CFG_OEO_HI                 0x00000000
#define EBC_CFG_OEO_PREVIOUS           0x00800000
#define EBC_CFG_EMC_MASK       	0x00400000
#define EBC_CFG_EMC_NONDEFAULT 	0x00000000
#define EBC_CFG_EMC_DEFAULT    	0x00400000
#define EBC_CFG_PME_MASK       	0x00200000
#define EBC_CFG_PME_DISABLE    	0x00000000
#define EBC_CFG_PME_ENABLE     	0x00200000
#define EBC_CFG_PMT_MASK               0x001F0000
#define EBC_CFG_PMT_ENCODE(n)  	((((unsigned long)(n))&0x1F)<<12)
#define EBC_CFG_PR_MASK                0x0000C000
#define EBC_CFG_PR_16                  0x00000000
#define EBC_CFG_PR_32                  0x00004000
#define EBC_CFG_PR_64                  0x00008000
#define EBC_CFG_PR_128                 0x0000C000

/*-----------------------------------------------------------------------------+
|  SDR 0 Bit Settings
+-----------------------------------------------------------------------------*/
#define SDR0_SDSTP0_ENG_MASK         0x80000000
#define SDR0_SDSTP0_ENG_PLLDIS       0x00000000
#define SDR0_SDSTP0_ENG_PLLENAB      0x80000000
#define SDR0_SDSTP0_ENG_ENCODE(n)    ((((unsigned long)(n))&0x01)<<31)
#define SDR0_SDSTP0_ENG_DECODE(n)    ((((unsigned long)(n))>>31)&0x01)
#define SDR0_SDSTP0_SRC_MASK         0x40000000
#define SDR0_SDSTP0_SRC_PLLOUTA      0x00000000
#define SDR0_SDSTP0_SRC_PLLOUTB      0x40000000
#define SDR0_SDSTP0_SRC_ENCODE(n)    ((((unsigned long)(n))&0x01)<<30)
#define SDR0_SDSTP0_SRC_DECODE(n)    ((((unsigned long)(n))>>30)&0x01)
#define SDR0_SDSTP0_SEL_MASK         0x38000000
#define SDR0_SDSTP0_SEL_PLLOUT       0x00000000
#define SDR0_SDSTP0_SEL_CPU          0x08000000
#define SDR0_SDSTP0_SEL_EBC          0x28000000
#define SDR0_SDSTP0_SEL_ENCODE(n)    ((((unsigned long)(n))&0x07)<<27)
#define SDR0_SDSTP0_SEL_DECODE(n)    ((((unsigned long)(n))>>27)&0x07)
#define SDR0_SDSTP0_TUNE_MASK        0x07FE0000
#define SDR0_SDSTP0_TUNE_ENCODE(n)   ((((unsigned long)(n))&0x3FF)<<17)
#define SDR0_SDSTP0_TUNE_DECODE(n)   ((((unsigned long)(n))>>17)&0x3FF)
#define SDR0_SDSTP0_FBDV_MASK        0x0001F000
#define SDR0_SDSTP0_FBDV_ENCODE(n)   ((((unsigned long)(n))&0x1F)<<12)
#define SDR0_SDSTP0_FBDV_DECODE(n)   ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
#define SDR0_SDSTP0_FWDVA_MASK       0x00000F00
#define SDR0_SDSTP0_FWDVA_ENCODE(n)  ((((unsigned long)(n))&0x0F)<<8)
#define SDR0_SDSTP0_FWDVA_DECODE(n)  ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
#define SDR0_SDSTP0_FWDVB_MASK       0x000000E0
#define SDR0_SDSTP0_FWDVB_ENCODE(n)  ((((unsigned long)(n))&0x07)<<5)
#define SDR0_SDSTP0_FWDVB_DECODE(n)  ((((((unsigned long)(n))>>5)-1)&0x07)+1)
#define SDR0_SDSTP0_PRBDV0_MASK      0x0000001C
#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
#define SDR0_SDSTP0_OPBDV0_MASK      0x00000003
#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)

#define SDR0_SDSTP1_LFBDV_MASK       0xFC000000
#define SDR0_SDSTP1_LFBDV_ENCODE(n)  ((((unsigned long)(n))&0x3F)<<26)
#define SDR0_SDSTP1_LFBDV_DECODE(n)  ((((unsigned long)(n))>>26)&0x3F)
#define SDR0_SDSTP1_EBCDV0_MASK      0x03000000
#define SDR0_SDSTP1_EBCDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
#define SDR0_SDSTP1_EBCDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
#define SDR0_SDSTP1_MALDV0_MASK      0x00C00000
#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
#define SDR0_SDSTP1_RW_MASK          0x00300000
#define SDR0_SDSTP1_RW_8BIT          0x00000000
#define SDR0_SDSTP1_RW_16BIT         0x00100000
#define SDR0_SDSTP1_RW_32BIT         0x00200000
#define SDR0_SDSTP1_RW_ENCODE(n)     ((((unsigned long)(n))&0x03)<<20)
#define SDR0_SDSTP1_RW_DECODE(n)     ((((unsigned long)(n))>>20)&0x03)
#define SDR0_SDSTP1_EARV_MASK        0x00080000
#define SDR0_SDSTP1_EARV_EBC         0x00000000
#define SDR0_SDSTP1_EARV_PCI         0x00080000
#define SDR0_SDSTP1_PAE_MASK         0x00040000
#define SDR0_SDSTP1_PAE_DISABLE      0x00000000
#define SDR0_SDSTP1_PAE_ENABLE       0x00040000
#define SDR0_SDSTP1_PAE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<18)
#define SDR0_SDSTP1_PAE_DECODE(n)    ((((unsigned long)(n))>>18)&0x01)
#define SDR0_SDSTP1_PHCE_MASK        0x00020000
#define SDR0_SDSTP1_PHCE_DISABLE     0x00000000
#define SDR0_SDSTP1_PHCE_ENABLE      0x00020000
#define SDR0_SDSTP1_PHCE_ENCODE(n)   ((((unsigned long)(n))&0x01)<<17)
#define SDR0_SDSTP1_PHCE_DECODE(n)   ((((unsigned long)(n))>>17)&0x01)
#define SDR0_SDSTP1_PISE_MASK        0x00010000
#define SDR0_SDSTP1_PISE_DISABLE     0x00000000
#define SDR0_SDSTP1_PISE_ENABLE      0x00010000
#define SDR0_SDSTP1_PISE_ENCODE(n)   ((((unsigned long)(n))&0x01)<<16)
#define SDR0_SDSTP1_PISE_DECODE(n)   ((((unsigned long)(n))>>16)&0x01)
#define SDR0_SDSTP1_PCWE_MASK        0x00008000
#define SDR0_SDSTP1_PCWE_DISABLE     0x00000000
#define SDR0_SDSTP1_PCWE_ENABLE      0x00008000
#define SDR0_SDSTP1_PCWE_ENCODE(n)   ((((unsigned long)(n))&0x01)<<15)
#define SDR0_SDSTP1_PCWE_DECODE(n)   ((((unsigned long)(n))>>15)&0x01)
#define SDR0_SDSTP1_PPIM_MASK        0x00008000
#define SDR0_SDSTP1_PPIM_ENCODE(n)   ((((unsigned long)(n))&0x0F)<<11)
#define SDR0_SDSTP1_PPIM_DECODE(n)   ((((unsigned long)(n))>>11)&0x0F)
#define SDR0_SDSTP1_PR64E_MASK       0x00000400
#define SDR0_SDSTP1_PR64E_DISABLE    0x00000000
#define SDR0_SDSTP1_PR64E_ENABLE     0x00000400
#define SDR0_SDSTP1_PR64E_ENCODE(n)  ((((unsigned long)(n))&0x01)<<10)
#define SDR0_SDSTP1_PR64E_DECODE(n)  ((((unsigned long)(n))>>10)&0x01)
#define SDR0_SDSTP1_PXFS_MASK        0x00000300
#define SDR0_SDSTP1_PXFS_HIGH        0x00000000
#define SDR0_SDSTP1_PXFS_MED         0x00000100
#define SDR0_SDSTP1_PXFS_LOW         0x00000200
#define SDR0_SDSTP1_PXFS_ENCODE(n)   ((((unsigned long)(n))&0x03)<<8)
#define SDR0_SDSTP1_PXFS_DECODE(n)   ((((unsigned long)(n))>>8)&0x03)
#define SDR0_SDSTP1_PDM_MASK         0x00000040
#define SDR0_SDSTP1_PDM_MULTIPOINT   0x00000000
#define SDR0_SDSTP1_PDM_P2P          0x00000040
#define SDR0_SDSTP1_PDM_ENCODE(n)    ((((unsigned long)(n))&0x01)<<6)
#define SDR0_SDSTP1_PDM_DECODE(n)    ((((unsigned long)(n))>>6)&0x01)
#define SDR0_SDSTP1_EPS_MASK         0x00000038
#define SDR0_SDSTP1_EPS_GROUP0       0x00000000
#define SDR0_SDSTP1_EPS_GROUP1       0x00000008
#define SDR0_SDSTP1_EPS_GROUP2       0x00000010
#define SDR0_SDSTP1_EPS_GROUP3       0x00000018
#define SDR0_SDSTP1_EPS_GROUP4       0x00000020
#define SDR0_SDSTP1_EPS_GROUP5       0x00000028
#define SDR0_SDSTP1_EPS_GROUP6       0x00000030
#define SDR0_SDSTP1_EPS_GROUP7       0x00000038
#define SDR0_SDSTP1_EPS_ENCODE(n)    ((((unsigned long)(n))&0x07)<<3)
#define SDR0_SDSTP1_EPS_DECODE(n)    ((((unsigned long)(n))>>3)&0x07)
#define SDR0_SDSTP1_RMII_MASK        0x00000004
#define SDR0_SDSTP1_RMII_100MBIT     0x00000000
#define SDR0_SDSTP1_RMII_10MBIT      0x00000004
#define SDR0_SDSTP1_RMII_ENCODE(n)   ((((unsigned long)(n))&0x01)<<2)
#define SDR0_SDSTP1_RMII_DECODE(n)   ((((unsigned long)(n))>>2)&0x01)
#define SDR0_SDSTP1_TRE_MASK         0x00000002
#define SDR0_SDSTP1_TRE_DISABLE      0x00000000
#define SDR0_SDSTP1_TRE_ENABLE       0x00000002
#define SDR0_SDSTP1_TRE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<1)
#define SDR0_SDSTP1_TRE_DECODE(n)    ((((unsigned long)(n))>>1)&0x01)
#define SDR0_SDSTP1_NTO1_MASK        0x00000001
#define SDR0_SDSTP1_NTO1_DISABLE     0x00000000
#define SDR0_SDSTP1_NTO1_ENABLE      0x00000001
#define SDR0_SDSTP1_NTO1_ENCODE(n)   ((((unsigned long)(n))&0x01)<<0)
#define SDR0_SDSTP1_NTO1_DECODE(n)   ((((unsigned long)(n))>>0)&0x01)

#define SDR0_EBC_RW_MASK             0x30000000
#define SDR0_EBC_RW_8BIT             0x00000000
#define SDR0_EBC_RW_16BIT            0x10000000
#define SDR0_EBC_RW_32BIT            0x20000000
#define SDR0_EBC_RW_ENCODE(n)        ((((unsigned long)(n))&0x03)<<28)
#define SDR0_EBC_RW_DECODE(n)        ((((unsigned long)(n))>>28)&0x03)

#define SDR0_UARTX_UXICS_MASK        0xF0000000
#define SDR0_UARTX_UXICS_PLB         0x20000000
#define SDR0_UARTX_UXEC_MASK         0x00800000
#define SDR0_UARTX_UXEC_INT          0x00000000
#define SDR0_UARTX_UXEC_EXT          0x00800000
#define SDR0_UARTX_UXDTE_MASK        0x00400000
#define SDR0_UARTX_UXDTE_DISABLE     0x00000000
#define SDR0_UARTX_UXDTE_ENABLE      0x00400000
#define SDR0_UARTX_UXDRE_MASK        0x00200000
#define SDR0_UARTX_UXDRE_DISABLE     0x00000000
#define SDR0_UARTX_UXDRE_ENABLE      0x00200000
#define SDR0_UARTX_UXDC_MASK         0x00100000
#define SDR0_UARTX_UXDC_NOTCLEARED   0x00000000
#define SDR0_UARTX_UXDC_CLEARED      0x00100000
#define SDR0_UARTX_UXDIV_MASK        0x000000FF
#define SDR0_UARTX_UXDIV_ENCODE(n)   ((((unsigned long)(n))&0xFF)<<0)
#define SDR0_UARTX_UXDIV_DECODE(n)   ((((((unsigned long)(n))>>0)-1)&0xFF)+1)

#define SDR0_CPU440_EARV_MASK        0x30000000
#define SDR0_CPU440_EARV_EBC         0x10000000
#define SDR0_CPU440_EARV_PCI         0x20000000
#define SDR0_CPU440_EARV_ENCODE(n)   ((((unsigned long)(n))&0x03)<<28)
#define SDR0_CPU440_EARV_DECODE(n)   ((((unsigned long)(n))>>28)&0x03)
#define SDR0_CPU440_NTO1_MASK        0x00000002
#define SDR0_CPU440_NTO1_NTOP        0x00000000
#define SDR0_CPU440_NTO1_NTO1        0x00000002
#define SDR0_CPU440_NTO1_ENCODE(n)   ((((unsigned long)(n))&0x01)<<1)
#define SDR0_CPU440_NTO1_DECODE(n)   ((((unsigned long)(n))>>1)&0x01)

#define SDR0_XCR_PAE_MASK            0x80000000
#define SDR0_XCR_PAE_DISABLE         0x00000000
#define SDR0_XCR_PAE_ENABLE          0x80000000
#define SDR0_XCR_PAE_ENCODE(n)       ((((unsigned long)(n))&0x01)<<31)
#define SDR0_XCR_PAE_DECODE(n)       ((((unsigned long)(n))>>31)&0x01)
#define SDR0_XCR_PHCE_MASK           0x40000000
#define SDR0_XCR_PHCE_DISABLE        0x00000000
#define SDR0_XCR_PHCE_ENABLE         0x40000000
#define SDR0_XCR_PHCE_ENCODE(n)      ((((unsigned long)(n))&0x01)<<30)
#define SDR0_XCR_PHCE_DECODE(n)      ((((unsigned long)(n))>>30)&0x01)
#define SDR0_XCR_PISE_MASK           0x20000000
#define SDR0_XCR_PISE_DISABLE        0x00000000
#define SDR0_XCR_PISE_ENABLE         0x20000000