sa-1100.h

F:worksip2440a board可启动u-boot-like.tar.gz F:worksip2440a board可启动u-boot-like.tar.gz

					/*  after frame (SFRM, 1st edge)   */
#define SSCR1_SClk1_2P	(SSCR1_SP*1)	/*  Sample Clock active 1/2 Period */
					/*  after frame (SFRM, 1st edge)   */
#define SSCR1_ECS	0x00000020	/* External Clock Select           */
#define SSCR1_IntClk	(SSCR1_ECS*0)	/*  Internal Clock                 */
#define SSCR1_ExtClk	(SSCR1_ECS*1)	/*  External Clock (GPIO [19])     */

#define SSDR_DATA	Fld (16, 0)	/* receive/transmit DATA FIFOs     */

#define SSSR_TNF	0x00000002	/* Transmit FIFO Not Full (read)   */
#define SSSR_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
#define SSSR_BSY	0x00000008	/* SSP BuSY (read)                 */
#define SSSR_TFS	0x00000010	/* Transmit FIFO 1/2-full or less  */
					/* Service request (read)          */
#define SSSR_RFS	0x00000020	/* Receive FIFO 1/2-full or more   */
					/* Service request (read)          */
#define SSSR_ROR	0x00000040	/* Receive FIFO Over-Run           */


/*
 * Operating System (OS) timer control registers
 *
 * Registers
 *    OSMR0     	Operating System (OS) timer Match Register 0
 *              	(read/write).
 *    OSMR1     	Operating System (OS) timer Match Register 1
 *              	(read/write).
 *    OSMR2     	Operating System (OS) timer Match Register 2
 *              	(read/write).
 *    OSMR3     	Operating System (OS) timer Match Register 3
 *              	(read/write).
 *    OSCR      	Operating System (OS) timer Counter Register
 *              	(read/write).
 *    OSSR      	Operating System (OS) timer Status Register
 *              	(read/write).
 *    OWER      	Operating System (OS) timer Watch-dog Enable Register
 *              	(read/write).
 *    OIER      	Operating System (OS) timer Interrupt Enable Register
 *              	(read/write).
 */

#define _OSMR(Nb)	        	/* OS timer Match Reg. [0..3]      */ \
			(0x90000000 + (Nb)*4)
#define _OSMR0  	_OSMR (0)	/* OS timer Match Reg. 0           */
#define _OSMR1  	_OSMR (1)	/* OS timer Match Reg. 1           */
#define _OSMR2  	_OSMR (2)	/* OS timer Match Reg. 2           */
#define _OSMR3  	_OSMR (3)	/* OS timer Match Reg. 3           */
#define _OSCR   	0x90000010	/* OS timer Counter Reg.           */
#define _OSSR   	0x90000014	/* OS timer Status Reg.            */
#define _OWER   	0x90000018	/* OS timer Watch-dog Enable Reg.  */
#define _OIER   	0x9000001C	/* OS timer Interrupt Enable Reg.  */

#if LANGUAGE == C
#define OSMR    	        	/* OS timer Match Reg. [0..3]      */ \
			((volatile Word *) io_p2v (_OSMR (0)))
#define OSMR0   	(OSMR [0])	/* OS timer Match Reg. 0           */
#define OSMR1   	(OSMR [1])	/* OS timer Match Reg. 1           */
#define OSMR2   	(OSMR [2])	/* OS timer Match Reg. 2           */
#define OSMR3   	(OSMR [3])	/* OS timer Match Reg. 3           */
#define OSCR    	        	/* OS timer Counter Reg.           */ \
			(*((volatile Word *) io_p2v (_OSCR)))
#define OSSR    	        	/* OS timer Status Reg.            */ \
			(*((volatile Word *) io_p2v (_OSSR)))
#define OWER    	        	/* OS timer Watch-dog Enable Reg.  */ \
			(*((volatile Word *) io_p2v (_OWER)))
#define OIER    	        	/* OS timer Interrupt Enable Reg.  */ \
			(*((volatile Word *) io_p2v (_OIER)))
#endif /* LANGUAGE == C */

#define OSSR_M(Nb)	        	/* Match detected [0..3]           */ \
			(0x00000001 << (Nb))
#define OSSR_M0 	OSSR_M (0)	/* Match detected 0                */
#define OSSR_M1 	OSSR_M (1)	/* Match detected 1                */
#define OSSR_M2 	OSSR_M (2)	/* Match detected 2                */
#define OSSR_M3 	OSSR_M (3)	/* Match detected 3                */

#define OWER_WME	0x00000001	/* Watch-dog Match Enable          */
					/* (set only)                      */

#define OIER_E(Nb)	        	/* match interrupt Enable [0..3]   */ \
			(0x00000001 << (Nb))
#define OIER_E0 	OIER_E (0)	/* match interrupt Enable 0        */
#define OIER_E1 	OIER_E (1)	/* match interrupt Enable 1        */
#define OIER_E2 	OIER_E (2)	/* match interrupt Enable 2        */
#define OIER_E3 	OIER_E (3)	/* match interrupt Enable 3        */


/*
 * Real-Time Clock (RTC) control registers
 *
 * Registers
 *    RTAR      	Real-Time Clock (RTC) Alarm Register (read/write).
 *    RCNR      	Real-Time Clock (RTC) CouNt Register (read/write).
 *    RTTR      	Real-Time Clock (RTC) Trim Register (read/write).
 *    RTSR      	Real-Time Clock (RTC) Status Register (read/write).
 *
 * Clocks
 *    frtx, Trtx	Frequency, period of the real-time clock crystal
 *              	(32.768 kHz nominal).
 *    frtc, Trtc	Frequency, period of the real-time clock counter
 *              	(1 Hz nominal).
 */

#define _RTAR   	0x90010000	/* RTC Alarm Reg.                  */
#define _RCNR   	0x90010004	/* RTC CouNt Reg.                  */
#define _RTTR   	0x90010008	/* RTC Trim Reg.                   */
#define _RTSR   	0x90010010	/* RTC Status Reg.                 */

#if LANGUAGE == C
#define RTAR    	        	/* RTC Alarm Reg.                  */ \
			(*((volatile Word *) io_p2v (_RTAR)))
#define RCNR    	        	/* RTC CouNt Reg.                  */ \
			(*((volatile Word *) io_p2v (_RCNR)))
#define RTTR    	        	/* RTC Trim Reg.                   */ \
			(*((volatile Word *) io_p2v (_RTTR)))
#define RTSR    	        	/* RTC Status Reg.                 */ \
			(*((volatile Word *) io_p2v (_RTSR)))
#endif /* LANGUAGE == C */

#define RTTR_C  	Fld (16, 0)	/* clock divider Count - 1         */
#define RTTR_D  	Fld (10, 16)	/* trim Delete count               */
					/* frtc = (1023*(C + 1) - D)*frtx/ */
					/*        (1023*(C + 1)^2)         */
					/* Trtc = (1023*(C + 1)^2)*Trtx/   */
					/*        (1023*(C + 1) - D)       */

#define RTSR_AL 	0x00000001	/* ALarm detected                  */
#define RTSR_HZ 	0x00000002	/* 1 Hz clock detected             */
#define RTSR_ALE	0x00000004	/* ALarm interrupt Enable          */
#define RTSR_HZE	0x00000008	/* 1 Hz clock interrupt Enable     */


/*
 * Power Manager (PM) control registers
 *
 * Registers
 *    PMCR      	Power Manager (PM) Control Register (read/write).
 *    PSSR      	Power Manager (PM) Sleep Status Register (read/write).
 *    PSPR      	Power Manager (PM) Scratch-Pad Register (read/write).
 *    PWER      	Power Manager (PM) Wake-up Enable Register
 *              	(read/write).
 *    PCFR      	Power Manager (PM) general ConFiguration Register
 *              	(read/write).
 *    PPCR      	Power Manager (PM) Phase-Locked Loop (PLL)
 *              	Configuration Register (read/write).
 *    PGSR      	Power Manager (PM) General-Purpose Input/Output (GPIO)
 *              	Sleep state Register (read/write, see GPIO pins).
 *    POSR      	Power Manager (PM) Oscillator Status Register (read).
 *
 * Clocks
 *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
 *              	or 3.5795 MHz).
 *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
 */

#define _PMCR   	0x90020000	/* PM Control Reg.                 */
#define _PSSR   	0x90020004	/* PM Sleep Status Reg.            */
#define _PSPR   	0x90020008	/* PM Scratch-Pad Reg.             */
#define _PWER   	0x9002000C	/* PM Wake-up Enable Reg.          */
#define _PCFR   	0x90020010	/* PM general ConFiguration Reg.   */
#define _PPCR   	0x90020014	/* PM PLL Configuration Reg.       */
#define _PGSR   	0x90020018	/* PM GPIO Sleep state Reg.        */
#define _POSR   	0x9002001C	/* PM Oscillator Status Reg.       */

#if LANGUAGE == C
#define PMCR    	        	/* PM Control Reg.                 */ \
			(*((volatile Word *) io_p2v (_PMCR)))
#define PSSR    	        	/* PM Sleep Status Reg.            */ \
			(*((volatile Word *) io_p2v (_PSSR)))
#define PSPR    	        	/* PM Scratch-Pad Reg.             */ \
			(*((volatile Word *) io_p2v (_PSPR)))
#define PWER    	        	/* PM Wake-up Enable Reg.          */ \
			(*((volatile Word *) io_p2v (_PWER)))
#define PCFR    	        	/* PM general ConFiguration Reg.   */ \
			(*((volatile Word *) io_p2v (_PCFR)))
#define PPCR    	        	/* PM PLL Configuration Reg.       */ \
			(*((volatile Word *) io_p2v (_PPCR)))
#define PGSR    	        	/* PM GPIO Sleep state Reg.        */ \
			(*((volatile Word *) io_p2v (_PGSR)))
#define POSR    	        	/* PM Oscillator Status Reg.       */ \
			(*((volatile Word *) io_p2v (_POSR)))

#elif LANGUAGE == Assembly
#define PMCR          	(io_p2v (_PMCR))
#define PSSR          	(io_p2v (_PSSR))
#define PSPR          	(io_p2v (_PSPR))
#define PWER          	(io_p2v (_PWER))
#define PCFR          	(io_p2v (_PCFR))
#define PPCR          	(io_p2v (_PPCR))
#define PGSR          	(io_p2v (_PGSR))
#define POSR          	(io_p2v (_POSR))

#endif /* LANGUAGE == C */

#define PMCR_SF 	0x00000001	/* Sleep Force (set only)          */

#define PSSR_SS 	0x00000001	/* Software Sleep                  */
#define PSSR_BFS	0x00000002	/* Battery Fault Status            */
					/* (BATT_FAULT)                    */
#define PSSR_VFS	0x00000004	/* Vdd Fault Status (VDD_FAULT)    */
#define PSSR_DH 	0x00000008	/* DRAM control Hold               */
#define PSSR_PH 	0x00000010	/* Peripheral control Hold         */

#define PWER_GPIO(Nb)	GPIO_GPIO (Nb)	/* GPIO [0..27] wake-up enable     */
#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable        */
#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable        */
#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable        */
#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable        */
#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable        */
#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable        */
#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable        */
#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable        */
#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable        */
#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable        */
#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable        */
#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable        */
#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable        */
#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable        */
#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable        */
#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable        */
#define PWER_GPIO16	PWER_GPIO (16)	/* GPIO [16] wake-up enable        */
#define PWER_GPIO17	PWER_GPIO (17)	/* GPIO [17] wake-up enable        */
#define PWER_GPIO18	PWER_GPIO (18)	/* GPIO [18] wake-up enable        */
#define PWER_GPIO19	PWER_GPIO (19)	/* GPIO [19] wake-up enable        */
#define PWER_GPIO20	PWER_GPIO (20)	/* GPIO [20] wake-up enable        */
#define PWER_GPIO21	PWER_GPIO (21)	/* GPIO [21] wake-up enable        */
#define PWER_GPIO22	PWER_GPIO (22)	/* GPIO [22] wake-up enable        */
#define PWER_GPIO23	PWER_GPIO (23)	/* GPIO [23] wake-up enable        */
#define PWER_GPIO24	PWER_GPIO (24)	/* GPIO [24] wake-up enable        */
#define PWER_GPIO25	PWER_GPIO (25)	/* GPIO [25] wake-up enable        */
#define PWER_GPIO26	PWER_GPIO (26)	/* GPIO [26] wake-up enable        */
#define PWER_GPIO27	PWER_GPIO (27)	/* GPIO [27] wake-up enable        */
#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */

#define PCFR_OPDE	0x00000001	/* Oscillator Power-Down Enable    */
#define PCFR_ClkRun	(PCFR_OPDE*0)	/*  Clock Running in sleep mode    */
#define PCFR_ClkStp	(PCFR_OPDE*1)	/*  Clock Stopped in sleep mode    */
#define PCFR_FP 	0x00000002	/* Float PCMCIA pins               */
#define PCFR_PCMCIANeg	(PCFR_FP*0)	/*  PCMCIA pins Negated (1)        */
#define PCFR_PCMCIAFlt	(PCFR_FP*1)	/*  PCMCIA pins Floating           */
#define PCFR_FS 	0x00000004	/* Float Static memory pins        */
#define PCFR_StMemNeg	(PCFR_FS*0)	/*  Static Memory pins Negated (1) */
#define PCFR_StMemFlt	(PCFR_FS*1)	/*  Static Memory pins Floating    */
#define PCFR_FO 	0x00000008	/* Force RTC oscillator            */
					/* (32.768 kHz) enable On          */

#define PPCR_CCF	Fld (5, 0)	/* CPU core Clock (CCLK) Freq.     */
#define PPCR_Fx16	        	/*  Freq. x 16 (fcpu = 16*fxtl)    */ \
			(0x00 << FShft (PPCR_CCF))
#define PPCR_Fx20	        	/*  Freq. x 20 (fcpu = 20*fxtl)    */ \
			(0x01 << FShft (PPCR_CCF))
#define PPCR_Fx24	        	/*  Freq. x 24 (fcpu = 24*fxtl)    */ \
			(0x02 << FShft (PPCR_CCF))
#define PPCR_Fx28	        	/*  Freq. x 28 (fcpu = 28*fxtl)    */ \
			(0x03 << FShft (PPCR_CCF))
#define PPCR_Fx32	        	/*  Freq. x 32 (fcpu = 32*fxtl)    */ \
			(0x04 << FShft (PPCR_CCF))
#define PPCR_Fx36	        	/*  Freq. x 36 (fcpu = 36*fxtl)    */ \
			(0x05 << FShft (PPCR_CCF))
#define PPCR_Fx40	        	/*  Freq. x 40 (fcpu = 40*fxtl)    */ \
			(0x06 << FShft (PPCR_CCF))
#define PPCR_Fx44	        	/*  Freq. x 44 (fcpu = 44*fxtl)    */ \
			(0x07 << FShft (PPCR_CCF))
#define PPCR_Fx48	        	/*  Freq. x 48 (fcpu = 48*fxtl)    */ \
			(0x08 << FShft (PPCR_CCF))
#define PPCR_Fx52	        	/*  Freq. x 52 (f