mpc8xx.h

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#define SCCR_DFNL011	0x00000300	/* Division by 16 	                */
#define SCCR_DFNL100	0x00000400	/* Division by 32 	                */
#define SCCR_DFNL101	0x00000500	/* Division by 64 	                */
#define SCCR_DFNL110	0x00000600	/* Division by 128 	                */
#define SCCR_DFNL111	0x00000700	/* Division by 256 (maximum)		*/
#define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
#define SCCR_DFNH110	0x000000D0	/* Division by 64 (maximum)		*/
#define SCCR_DFNH111	0x000000E0	/* reserved				*/
#define SCCR_DFLCD000	0x00000000	/* Division by 1 (default = minimum)	*/
#define SCCR_DFLCD001	0x00000004	/* Division by 2			*/
#define SCCR_DFLCD010	0x00000008	/* Division by 4			*/
#define SCCR_DFLCD011	0x0000000C	/* Division by 8			*/
#define SCCR_DFLCD100	0x00000010	/* Division by 16			*/
#define SCCR_DFLCD101	0x00000014	/* Division by 32			*/
#define SCCR_DFLCD110	0x00000018	/* Division by 64 (maximum)		*/
#define SCCR_DFLCD111	0x0000001C	/* reserved				*/
#define SCCR_DFALCD00	0x00000000	/* Division by 1 (default = minimum)	*/
#define SCCR_DFALCD01	0x00000001	/* Division by 3			*/
#define SCCR_DFALCD10	0x00000002	/* Division by 5			*/
#define SCCR_DFALCD11	0x00000003	/* Division by 7 (maximum)		*/


/*-----------------------------------------------------------------------
 * BR - Memory Controler: Base Register					16-9
 */
#define BR_BA_MSK	0xFFFF8000	/* Base Address Mask			*/
#define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
#define BR_PS_MSK	0x00000C00	/* Port Size Mask			*/
#define BR_PS_32	0x00000000	/* 32 bit port size			*/
#define BR_PS_16	0x00000800	/* 16 bit port size			*/
#define BR_PS_8		0x00000400	/*  8 bit port size			*/
#define BR_PARE		0x00000200	/* Parity Enable			*/
#define BR_WP		0x00000100	/* Write Protect			*/
#define BR_MS_MSK	0x000000C0	/* Machine Select Mask			*/
#define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
#define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
#define BR_MS_UPMB	0x000000C0	/* U.P.M.B Machine Select		*/
#define BR_V		0x00000001	/* Bank Valid				*/

/*-----------------------------------------------------------------------
 * OR - Memory Controler: Option Register				16-11
 */
#define OR_AM_MSK	0xFFFF8000	/* Address Mask Mask			*/
#define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
#define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
					/* Address Multiplex			*/
#define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask	*/
#define OR_ACS_DIV1	0x00000000	/* CS is output at the same time	*/
#define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later	*/
#define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later	*/
#define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
#define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
#define OR_BI		0x00000100	/* Burst inhibit			*/
#define OR_SCY_MSK	0x000000F0	/* Cycle Lenght in Clocks		*/
#define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
#define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
#define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
#define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
#define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
#define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
#define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
#define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
#define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
#define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
#define OR_SCY_10_CLK	0x000000A0	/* 10 clock cycles wait states		*/
#define OR_SCY_11_CLK	0x000000B0	/* 11 clock cycles wait states		*/
#define OR_SCY_12_CLK	0x000000C0	/* 12 clock cycles wait states		*/
#define OR_SCY_13_CLK	0x000000D0	/* 13 clock cycles wait states		*/
#define OR_SCY_14_CLK	0x000000E0	/* 14 clock cycles wait states		*/
#define OR_SCY_15_CLK	0x000000F0	/* 15 clock cycles wait states		*/
#define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
#define OR_TRLX		0x00000004	/* Timing Relaxed			*/
#define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/


/*-----------------------------------------------------------------------
 * MPTPR - Memory Periodic Timer Prescaler Register			16-17
 */
#define MPTPR_PTP_MSK	0xFF00		/* Periodic Timers Prescaler Mask	*/
#define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2			*/
#define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4			*/
#define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8			*/
#define MPTPR_PTP_DIV16 0x0400		/* BRGCLK divided by 16			*/
#define MPTPR_PTP_DIV32 0x0200		/* BRGCLK divided by 32			*/
#define MPTPR_PTP_DIV64 0x0100		/* BRGCLK divided by 64			*/

/*-----------------------------------------------------------------------
 * MCR - Memory Command Register
 */
#define MCR_OP_WRITE	0x00000000	/* WRITE command			*/
#define MCR_OP_READ	0x40000000	/* READ	 command			*/
#define MCR_OP_RUN	0x80000000	/* RUN	 command			*/
#define MCR_UPM_A	0x00000000	/* Select UPM A				*/
#define MCR_UPM_B	0x00800000	/* Select UPM B				*/
#define MCR_MB_CS0	0x00000000	/* Use Chip Select /CS0			*/
#define MCR_MB_CS1	0x00002000	/* Use Chip Select /CS1			*/
#define MCR_MB_CS2	0x00004000	/* Use Chip Select /CS2			*/
#define MCR_MB_CS3	0x00006000	/* Use Chip Select /CS3			*/
#define MCR_MB_CS4	0x00008000	/* Use Chip Select /CS4			*/
#define MCR_MB_CS5	0x0000A000	/* Use Chip Select /CS5			*/
#define MCR_MB_CS6	0x0000C000	/* Use Chip Select /CS6			*/
#define MCR_MB_CS7	0x0000E000	/* Use Chip Select /CS7			*/
#define MCR_MLCF(n)	(((n)&0xF)<<8)	/* Memory Command Loop Count Field	*/
#define MCR_MAD(addr)	((addr)&0x3F)	/* Memory Array Index			*/

/*-----------------------------------------------------------------------
 * Machine A Mode Register						16-13
 */
#define MAMR_PTA_MSK	0xFF000000	/* Periodic Timer A period mask		*/
#define MAMR_PTA_SHIFT	0x00000018	/* Periodic Timer A period shift	*/
#define MAMR_PTAE	0x00800000	/* Periodic Timer A Enable		*/
#define MAMR_AMA_MSK	0x00700000	/* Addess Multiplexing size A		*/
#define MAMR_AMA_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
#define MAMR_AMA_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
#define MAMR_AMA_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
#define MAMR_AMA_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
#define MAMR_AMA_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
#define MAMR_AMA_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
#define MAMR_DSA_MSK	0x00060000	/* Disable Timer period mask		*/
#define MAMR_DSA_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
#define MAMR_DSA_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
#define MAMR_DSA_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
#define MAMR_DSA_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
#define MAMR_G0CLA_MSK	0x0000E000	/* General Line 0 Control A		*/
#define MAMR_G0CLA_A12	0x00000000	/* General Line 0 : A12			*/
#define MAMR_G0CLA_A11	0x00002000	/* General Line 0 : A11			*/
#define MAMR_G0CLA_A10	0x00004000	/* General Line 0 : A10			*/
#define MAMR_G0CLA_A9	0x00006000	/* General Line 0 : A9			*/
#define MAMR_G0CLA_A8	0x00008000	/* General Line 0 : A8			*/
#define MAMR_G0CLA_A7	0x0000A000	/* General Line 0 : A7			*/
#define MAMR_G0CLA_A6	0x0000C000	/* General Line 0 : A6			*/
#define MAMR_G0CLA_A5	0x0000E000	/* General Line 0 : A5			*/
#define MAMR_GPL_A4DIS	0x00001000	/* GPL_A4 ouput line Disable		*/
#define MAMR_RLFA_MSK	0x00000F00	/* Read Loop Field A mask		*/
#define MAMR_RLFA_1X	0x00000100	/* The Read Loop is executed 1 time	*/
#define MAMR_RLFA_2X	0x00000200	/* The Read Loop is executed 2 times	*/
#define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times	*/
#define MAMR_RLFA_4X	0x00000400	/* The Read Loop is executed 4 times	*/
#define MAMR_RLFA_5X	0x00000500	/* The Read Loop is executed 5 times	*/
#define MAMR_RLFA_6X	0x00000600	/* The Read Loop is executed 6 times	*/
#define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times	*/
#define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times	*/
#define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times	*/
#define MAMR_RLFA_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
#define MAMR_RLFA_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
#define MAMR_RLFA_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
#define MAMR_RLFA_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
#define MAMR_RLFA_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
#define MAMR_RLFA_15X	0x00000F00	/* The Read Loop is executed 15 times	*/
#define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times	*/
#define MAMR_WLFA_MSK	0x000000F0	/* Write Loop Field A mask		*/
#define MAMR_WLFA_1X	0x00000010	/* The Write Loop is executed 1 time	*/
#define MAMR_WLFA_2X	0x00000020	/* The Write Loop is executed 2 times	*/
#define MAMR_WLFA_3X	0x00000030	/* The Write Loop is executed 3 times	*/
#define MAMR_WLFA_4X	0x00000040	/* The Write Loop is executed 4 times	*/
#define MAMR_WLFA_5X	0x00000050	/* The Write Loop is executed 5 times	*/
#define MAMR_WLFA_6X	0x00000060	/* The Write Loop is executed 6 times	*/
#define MAMR_WLFA_7X	0x00000070	/* The Write Loop is executed 7 times	*/
#define MAMR_WLFA_8X	0x00000080	/* The Write Loop is executed 8 times	*/
#define MAMR_WLFA_9X	0x00000090	/* The Write Loop is executed 9 times	*/
#define MAMR_WLFA_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
#define MAMR_WLFA_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
#define MAMR_WLFA_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
#define MAMR_WLFA_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
#define MAMR_WLFA_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
#define MAMR_WLFA_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
#define MAMR_WLFA_16X	0x00000000	/* The Write Loop is executed 16 times	*/
#define MAMR_TLFA_MSK	0x0000000F	/* Timer Loop Field A mask		*/
#define MAMR_TLFA_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
#define MAMR_TLFA_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
#define MAMR_TLFA_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
#define MAMR_TLFA_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
#define MAMR_TLFA_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
#define MAMR_TLFA_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
#define MAMR_TLFA_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
#define MAMR_TLFA_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
#define MAMR_TLFA_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
#define MAMR_TLFA_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
#define MAMR_TLFA_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
#define MAMR_TLFA_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
#define MAMR_TLFA_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
#define MAMR_TLFA_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
#define MAMR_TLFA_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
#define MAMR_TLFA_16X	0x00000000	/* The Timer Loop is executed 16 times	*/

/*-----------------------------------------------------------------------
 * Machine B Mode Register						16-13
 */
#define MBMR_PTB_MSK	0xFF000000	/* Periodic Timer B period mask		*/
#define MBMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
#define MBMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
#define MBMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
#define MBMR_AMB_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
#define MBMR_AMB_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
#define MBMR_AMB_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
#define MBMR_AMB_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
#define MBMR_AMB_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
#define MBMR_AMB_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
#define MBMR_DSB_MSK	0x00060000	/* Disable Timer period mask		*/
#define MBMR_DSB_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
#define MBMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
#define MBMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
#define MBMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
#define MBMR_G0CLB_MSK	0x0000E000	/* General Line 0 Control B		*/
#define MBMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
#define MBMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
#define MBMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
#define MBMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
#define MBMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
#define MBMR_G0CLB_A7	0x0000A000	/* General Line 0 : A7			*/
#define MBMR_G0CLB_A6	0x0000C000	/* General Line 0 : A6			*/
#define MBMR_G0CLB_A5	0x0000E000	/* General Line 0 : A5			*/