mpc8xx.h

F:worksip2440a board可启动u-boot-like.tar.gz F:worksip2440a board可启动u-boot-like.tar.gz

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8xx.h
 *
 * MPC8xx specific definitions
 */

#ifndef __MPCXX_H__
#define __MPCXX_H__


/*-----------------------------------------------------------------------
 * Exception offsets (PowerPC standard)
 */
#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/


/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control Register				11-9
 */
#define SYPCR_SWTC	0xFFFF0000	/* Software Watchdog Timer Count	*/
#define SYPCR_BMT	0x0000FF00	/* Bus Monitor Timing			*/
#define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select	*/
#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale		*/

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration Register				11-6
 */
#define SIUMCR_EARB	0x80000000	/* External Arbitration			*/
#define SIUMCR_EARP0	0x00000000	/* External Arbi. Request priority 0	*/
#define SIUMCR_EARP1	0x10000000	/* External Arbi. Request priority 1	*/
#define SIUMCR_EARP2	0x20000000	/* External Arbi. Request priority 2	*/
#define SIUMCR_EARP3	0x30000000	/* External Arbi. Request priority 3	*/
#define SIUMCR_EARP4	0x40000000	/* External Arbi. Request priority 4	*/
#define SIUMCR_EARP5	0x50000000	/* External Arbi. Request priority 5	*/
#define SIUMCR_EARP6	0x60000000	/* External Arbi. Request priority 6	*/
#define SIUMCR_EARP7	0x70000000	/* External Arbi. Request priority 7	*/
#define SIUMCR_DSHW	0x00800000	/* Data Showcycles			*/
#define SIUMCR_DBGC00	0x00000000	/* Debug pins configuration		*/
#define SIUMCR_DBGC01	0x00200000	/* - " -				*/
#define SIUMCR_DBGC10	0x00400000	/* - " -				*/
#define SIUMCR_DBGC11	0x00600000	/* - " -				*/
#define SIUMCR_DBPC00	0x00000000	/* Debug Port pins Config.		*/
#define SIUMCR_DBPC01	0x00080000	/* - " -				*/
#define SIUMCR_DBPC10	0x00100000	/* - " -				*/
#define SIUMCR_DBPC11	0x00180000	/* - " -				*/
#define SIUMCR_FRC	0x00020000	/* FRZ pin Configuration		*/
#define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
#define SIUMCR_PNCS	0x00008000	/* Parity Non-mem Crtl reg		*/
#define SIUMCR_OPAR	0x00004000	/* Odd Parity				*/
#define SIUMCR_DPC	0x00002000	/* Data Parity pins Config.		*/
#define SIUMCR_MPRE	0x00001000	/* Multi CPU Reserva. Enable		*/
#define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
#define SIUMCR_MLRC01	0x00000400	/* - " -				*/
#define SIUMCR_MLRC10	0x00000800	/* - " -				*/
#define SIUMCR_MLRC11	0x00000C00	/* - " -				*/
#define SIUMCR_AEME	0x00000200	/* Asynchro External Master		*/
#define SIUMCR_SEME	0x00000100	/* Synchro External Master		*/
#define SIUMCR_BSC	0x00000080	/* Byte Select Configuration		*/
#define SIUMCR_GB5E	0x00000040	/* GPL_B(5) Enable			*/
#define SIUMCR_B2DD	0x00000020	/* Bank 2 Double Drive			*/
#define SIUMCR_B3DD	0x00000010	/* Bank 3 Double Drive			*/

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control Register			11-26
 */
#define TBSCR_TBIRQ7	0x8000		/* Time Base Interrupt Request 7	*/
#define TBSCR_TBIRQ6	0x4000		/* Time Base Interrupt Request 6	*/
#define TBSCR_TBIRQ5	0x2000		/* Time Base Interrupt Request 5	*/
#define TBSCR_TBIRQ4	0x1000		/* Time Base Interrupt Request 4	*/
#define TBSCR_TBIRQ3	0x0800		/* Time Base Interrupt Request 3	*/
#define TBSCR_TBIRQ2	0x0400		/* Time Base Interrupt Request 2	*/
#define TBSCR_TBIRQ1	0x0200		/* Time Base Interrupt Request 1	*/
#define TBSCR_TBIRQ0	0x0100		/* Time Base Interrupt Request 0	*/
#if 0	/* already in asm/8xx_immap.h */
#define TBSCR_REFA	0x0080		/* Reference Interrupt Status A		*/
#define TBSCR_REFB	0x0040		/* Reference Interrupt Status B		*/
#define TBSCR_REFAE	0x0008		/* Second Interrupt Enable A		*/
#define TBSCR_REFBE	0x0004		/* Second Interrupt Enable B		*/
#define TBSCR_TBF	0x0002		/* Time Base Freeze			*/
#define TBSCR_TBE	0x0001		/* Time Base Enable			*/
#endif

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control Register		11-31
 */
#undef	PISCR_PIRQ			/* TBD					*/
#define PISCR_PITF	0x0002		/* Periodic Interrupt Timer Freeze	*/
#if 0	/* already in asm/8xx_immap.h */
#define PISCR_PS	0x0080		/* Periodic interrupt Status		*/
#define PISCR_PIE	0x0004		/* Periodic Interrupt Enable		*/
#define PISCR_PTE	0x0001		/* Periodic Timer Enable		*/
#endif

/*-----------------------------------------------------------------------
 * RSR - Reset Status Register						 5-4
 */
#define RSR_JTRS	0x01000000	/* JTAG Reset Status		*/
#define RSR_DBSRS	0x02000000	/* Debug Port Soft Reset Status */
#define RSR_DBHRS	0x04000000	/* Debug Port Hard Reset Status */
#define RSR_CSRS	0x08000000	/* Check Stop Reset Status	*/
#define RSR_SWRS	0x10000000	/* Software Watchdog Reset Status*/
#define RSR_LLRS	0x20000000	/* Loss-of-Lock Reset Status	*/
#define RSR_ESRS	0x40000000	/* External Soft Reset Status	*/
#define RSR_EHRS	0x80000000	/* External Hard Reset Status	*/

#define RSR_ALLBITS	(RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS)

/*-----------------------------------------------------------------------
 * Newer chips (MPC866 family and MPC87x/88x family) have different
 * clock distribution system. Their IMMR lower half is >= 0x0800
 */
#define MPC8xx_NEW_CLK 0x0800

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
 */
/* Newer chips (MPC866/87x/88x et al) defines */
#define PLPRCR_MFN_MSK	0xF8000000	/* Multiplication factor numerator bits */
#define PLPRCR_MFN_SHIFT	27	/* Multiplication factor numerator shift*/
#define PLPRCR_MFD_MSK	0x07C00000	/* Multiplication factor denominator bits */
#define PLPRCR_MFD_SHIFT	22	/* Multiplication factor denominator shift*/
#define PLPRCR_S_MSK	0x00300000	/* Multiplication factor integer bits	*/
#define PLPRCR_S_SHIFT		20	/* Multiplication factor integer shift	*/
#define PLPRCR_MFI_MSK	0x000F0000	/* Multiplication factor integer bits	*/
#define PLPRCR_MFI_SHIFT	16	/* Multiplication factor integer shift	*/

#define PLPRCR_PDF_MSK	0x0000001E	/* Predivision Factor bits		*/
#define PLPRCR_PDF_SHIFT	 1	/* Predivision Factor shift value	*/
#define PLPRCR_DBRMO	0x00000001	/* DPLL BRM Order bit			*/

/* Multiplication factor + PDF bits */
#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \
			  PLPRCR_MFD_MSK | \
			  PLPRCR_S_MSK	 | \
			  PLPRCR_MFI_MSK | \
			  PLPRCR_PDF_MSK)

/* Older chips (MPC860/862 et al) defines */
#define PLPRCR_MF_MSK	0xFFF00000	/* Multiplication factor bits		*/
#define PLPRCR_MF_SHIFT		20	/* Multiplication factor shift value	*/

#define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
#define PLPRCR_TMIST	0x00001000	/* Timers Interrupt Status		*/

#define PLPRCR_LPM_MSK	0x00000300	/* Low Power Mode mask			*/
#define PLPRCR_LPM_NORMAL 0x00000000	/* normal power management mode		*/
#define PLPRCR_LPM_DOZE	  0x00000100	/* doze power management mode		*/
#define PLPRCR_LPM_SLEEP  0x00000200	/* sleep power management mode		*/
#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode		*/
#define PLPRCR_LPM_DOWN	  0x00000300	/* down power management mode		*/

/* Common defines */
#define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
#define PLPRCR_CSRC	0x00000400	/* Clock Source				*/

#define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
#define PLPRCR_LOLRE	0x00000040	/* Loss Of Lock Reset Enable		*/
#define PLPRCR_FIOPD	0x00000020	/* Force I/O Pull Down			*/

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register			15-27
 */
#define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
#define SCCR_COM01	0x20000000	/* half strength CLKOUT output buffer	*/
#define SCCR_COM10	0x40000000	/* reserved				*/
#define SCCR_COM11	0x60000000	/* CLKOUT output buffer disabled	*/
#define SCCR_TBS	0x02000000	/* Time Base Source			*/
#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide			*/
#define SCCR_RTSEL	0x00800000	/* RTC circuit input source select	*/
#define SCCR_CRQEN	0x00400000	/* CPM Request Enable			*/
#define SCCR_PRQEN	0x00200000	/* Power Management Request Enable	*/
#define SCCR_EBDF00	0x00000000	/* CLKOUT is GCLK2 / 1 (normal op.)	*/
#define SCCR_EBDF01	0x00020000	/* CLKOUT is GCLK2 / 2			*/
#define SCCR_EBDF10	0x00040000	/* reserved				*/
#define SCCR_EBDF11	0x00060000	/* reserved				*/
#define SCCR_DFSYNC00	0x00000000	/* SyncCLK division by 1 (normal op.)	*/
#define SCCR_DFSYNC01	0x00002000	/* SyncCLK division by 4		*/
#define SCCR_DFSYNC10	0x00004000	/* SyncCLK division by 16		*/
#define SCCR_DFSYNC11	0x00006000	/* SyncCLK division by 64		*/
#define SCCR_DFBRG00	0x00000000	/* BRGCLK division by 1 (normal op.)	*/
#define SCCR_DFBRG01	0x00000800	/* BRGCLK division by 4			*/
#define SCCR_DFBRG10	0x00001000	/* BRGCLK division by 16		*/
#define SCCR_DFBRG11	0x00001800	/* BRGCLK division by 64		*/
#define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
#define SCCR_DFNL001	0x00000100	/* Division by 4 	                */
#define SCCR_DFNL010	0x00000200	/* Division by 8 	                */