mpc8220.h

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#define GPT_TMS_PWM	    0x03	/* PWM Capture Enable */
#define GPT_TMS_SGPIO	    0x04	/* PWM Capture Enable */

#define GPT_PWM_WIDTH(x)    (x & 0xffff)

/* Status */
#define GPT_STA_CAPTURE(x)  (x & 0xffff)/* Read of internal counter */

#define GPT_OVFPIN_OVF(x)   (x & 0x70)	/* Internal counter roll over */
#define GPT_OVFPIN_PIN	    0x01	/* Input pin - Timer 0 and 1 */

#define GPT_INT_TEXP	    0x08	/* Timer Expired in Internal Timer mode */
#define GPT_INT_PWMP	    0x04	/* PWM end of period occurred */
#define GPT_INT_COMP	    0x02	/* OC reference event occurred */
#define GPT_INT_CAPT	    0x01	/* IC reference event occurred */

/* ------------------------------------------------------------------------ */
/*
 * Port configuration
 */
#define CFG_FEC1_PORT0_CONFIG	0x00000000
#define CFG_FEC1_PORT1_CONFIG	0x00000000
#define CFG_1284_PORT0_CONFIG	0x55555557
#define CFG_1284_PORT1_CONFIG	0x80000000
#define CFG_FEC2_PORT2_CONFIG	0x00000000
#define CFG_PEV_PORT2_CONFIG	0x55555540
#define CFG_GP0_PORT0_CONFIG	0xaaaaaaa0
#define CFG_GP1_PORT2_CONFIG	0xaaaaa000
#define CFG_PSC_PORT3_CONFIG	0x00000000
#define CFG_CS2_PORT3_CONFIG	0x10000000
#define CFG_CS3_PORT3_CONFIG	0x40000000
#define CFG_CS4_PORT3_CONFIG	0x00000400
#define CFG_CS5_PORT3_CONFIG	0x00000100
#define CFG_I2C_PORT3_CONFIG	0x003c0000

/* ------------------------------------------------------------------------ */
/*
 * DRAM configuration
 */

/* Field definitions for the control register */
#define CTL_MODE_ENABLE_SHIFT	    31
#define CTL_CKE_SHIFT		    30
#define CTL_DDR_SHIFT		    29
#define CTL_REFRESH_SHIFT	    28
#define CTL_ADDRMUX_SHIFT	    24
#define CTL_PRECHARGE_SHIFT	    23
#define CTL_DRIVE_RULE_SHIFT	    22
#define CTL_REFRESH_INTERVAL_SHIFT  16
#define CTL_DQSOEN_SHIFT	    8
#define CTL_BUFFERED_SHIFT	    4
#define CTL_REFRESH_CMD_SHIFT	    2
#define CTL_PRECHARGE_CMD_SHIFT	    1

#define CTL_MODE_ENABLE		    (1<<CTL_MODE_ENABLE_SHIFT)
#define CTL_CKE_HIGH		    (1<<CTL_CKE_SHIFT)
#define CTL_DDR_MODE		    (1<<CTL_DDR_SHIFT)
#define CTL_REFRESH_ENABLE	    (1<<CTL_REFRESH_SHIFT)
#define CTL_ADDRMUX(value)	    ((value)<<CTL_ADDRMUX_SHIFT)
#define CTL_A8PRECHARGE		    (1<<CTL_PRECHARGE_SHIFT)
#define CTL_REFRESH_INTERVAL(value) ((value)<<CTL_REFRESH_INTERVAL_SHIFT)
#define CTL_DQSOEN(value)	    ((value)<<CTL_DQSOEN_SHIFT)
#define CTL_BUFFERED		    (1<<CTL_BUFFERED_SHIFT)
#define CTL_REFRESH_CMD		    (1<<CTL_REFRESH_CMD_SHIFT)
#define CTL_PRECHARGE_CMD	    (1<<CTL_PRECHARGE_CMD_SHIFT)

/* Field definitions for config register 1 */

#define CFG1_SRD2RWP_SHIFT	    28
#define CFG1_SWT2RWP_SHIFT	    24
#define CFG1_RLATENCY_SHIFT	    20
#define CFG1_ACT2WR_SHIFT	    16
#define CFG1_PRE2ACT_SHIFT	    12
#define CFG1_REF2ACT_SHIFT	    8
#define CFG1_WLATENCY_SHIFT	    4

#define CFG1_SRD2RWP(value)	    ((value)<<CFG1_SRD2RWP_SHIFT)
#define CFG1_SWT2RWP(value)	    ((value)<<CFG1_SWT2RWP_SHIFT)
#define CFG1_RLATENCY(value)	    ((value)<<CFG1_RLATENCY_SHIFT)
#define CFG1_ACT2WR(value)	    ((value)<<CFG1_ACT2WR_SHIFT)
#define CFG1_PRE2ACT(value)	    ((value)<<CFG1_PRE2ACT_SHIFT)
#define CFG1_REF2ACT(value)	    ((value)<<CFG1_REF2ACT_SHIFT)
#define CFG1_WLATENCY(value)	    ((value)<<CFG1_WLATENCY_SHIFT)

/* Field definitions for config register 2 */
#define CFG2_BRD2RP_SHIFT	    28
#define CFG2_BWT2RWP_SHIFT	    24
#define CFG2_BRD2WT_SHIFT	    20
#define CFG2_BURSTLEN_SHIFT	    16

#define CFG2_BRD2RP(value)	    ((value)<<CFG2_BRD2RP_SHIFT)
#define CFG2_BWT2RWP(value)	    ((value)<<CFG2_BWT2RWP_SHIFT)
#define CFG2_BRD2WT(value)	    ((value)<<CFG2_BRD2WT_SHIFT)
#define CFG2_BURSTLEN(value)	    ((value)<<CFG2_BURSTLEN_SHIFT)

/* Field definitions for the mode/extended mode register - mode
 * register access
 */
#define MODE_REG_SHIFT		    30
#define MODE_OPMODE_SHIFT	    25
#define MODE_CL_SHIFT		    22
#define MODE_BT_SHIFT		    21
#define MODE_BURSTLEN_SHIFT	    18
#define MODE_CMD_SHIFT		    16

#define MODE_MODE		    0
#define MODE_OPMODE(value)	    ((value)<<MODE_OPMODE_SHIFT)
#define MODE_CL(value)		    ((value)<<MODE_CL_SHIFT)
#define MODE_BT_INTERLEAVED	    (1<<MODE_BT_SHIFT)
#define MODE_BT_SEQUENTIAL	    (0<<MODE_BT_SHIFT)
#define MODE_BURSTLEN(value)	    ((value)<<MODE_BURSTLEN_SHIFT)
#define MODE_CMD		    (1<<MODE_CMD_SHIFT)

#define MODE_BURSTLEN_8		    3
#define MODE_BURSTLEN_4		    2
#define MODE_BURSTLEN_2		    1

#define MODE_CL_2		    2
#define MODE_CL_2p5		    6
#define MODE_OPMODE_NORMAL	    0
#define MODE_OPMODE_RESETDLL	    2


/* Field definitions for the mode/extended mode register - extended
 * mode register access
 */
#define MODE_X_DLL_SHIFT	    18 /* DLL enable/disable */
#define MODE_X_DS_SHIFT		    19 /* Drive strength normal/reduced */
#define MODE_X_QFC_SHIFT	    20 /* QFC function (whatever that is) */
#define MODE_X_OPMODE_SHIFT	    21

#define MODE_EXTENDED		    (1<<MODE_REG_SHIFT)
#define MODE_X_DLL_ENABLE	    0
#define MODE_X_DLL_DISABLE	    (1<<MODE_X_DLL_SHIFT)
#define MODE_X_DS_NORMAL	    0
#define MODE_X_DS_REDUCED	    (1<<MODE_X_DS_SHIFT)
#define MODE_X_QFC_DISABLED	    0
#define MODE_X_OPMODE(value)	    ((value)<<MODE_X_OPMODE_SHIFT)

#ifndef __ASSEMBLY__
/*
 * DMA control/status registers.
 */
struct mpc8220_dma {
    u32 taskBar;	/* DMA + 0x00 */
    u32 currentPointer; /* DMA + 0x04 */
    u32 endPointer;	/* DMA + 0x08 */
    u32 variablePointer;/* DMA + 0x0c */

    u8 IntVect1;	/* DMA + 0x10 */
    u8 IntVect2;	/* DMA + 0x11 */
    u16 PtdCntrl;	/* DMA + 0x12 */

    u32 IntPend;	/* DMA + 0x14 */
    u32 IntMask;	/* DMA + 0x18 */

    u16 tcr_0;		/* DMA + 0x1c */
    u16 tcr_1;		/* DMA + 0x1e */
    u16 tcr_2;		/* DMA + 0x20 */
    u16 tcr_3;		/* DMA + 0x22 */
    u16 tcr_4;		/* DMA + 0x24 */
    u16 tcr_5;		/* DMA + 0x26 */
    u16 tcr_6;		/* DMA + 0x28 */
    u16 tcr_7;		/* DMA + 0x2a */
    u16 tcr_8;		/* DMA + 0x2c */
    u16 tcr_9;		/* DMA + 0x2e */
    u16 tcr_a;		/* DMA + 0x30 */
    u16 tcr_b;		/* DMA + 0x32 */
    u16 tcr_c;		/* DMA + 0x34 */
    u16 tcr_d;		/* DMA + 0x36 */
    u16 tcr_e;		/* DMA + 0x38 */
    u16 tcr_f;		/* DMA + 0x3a */

    u8 IPR0;		/* DMA + 0x3c */
    u8 IPR1;		/* DMA + 0x3d */
    u8 IPR2;		/* DMA + 0x3e */
    u8 IPR3;		/* DMA + 0x3f */
    u8 IPR4;		/* DMA + 0x40 */
    u8 IPR5;		/* DMA + 0x41 */
    u8 IPR6;		/* DMA + 0x42 */
    u8 IPR7;		/* DMA + 0x43 */
    u8 IPR8;		/* DMA + 0x44 */
    u8 IPR9;		/* DMA + 0x45 */
    u8 IPR10;		/* DMA + 0x46 */
    u8 IPR11;		/* DMA + 0x47 */
    u8 IPR12;		/* DMA + 0x48 */
    u8 IPR13;		/* DMA + 0x49 */
    u8 IPR14;		/* DMA + 0x4a */
    u8 IPR15;		/* DMA + 0x4b */
    u8 IPR16;		/* DMA + 0x4c */
    u8 IPR17;		/* DMA + 0x4d */
    u8 IPR18;		/* DMA + 0x4e */
    u8 IPR19;		/* DMA + 0x4f */
    u8 IPR20;		/* DMA + 0x50 */
    u8 IPR21;		/* DMA + 0x51 */
    u8 IPR22;		/* DMA + 0x52 */
    u8 IPR23;		/* DMA + 0x53 */
    u8 IPR24;		/* DMA + 0x54 */
    u8 IPR25;		/* DMA + 0x55 */
    u8 IPR26;		/* DMA + 0x56 */
    u8 IPR27;		/* DMA + 0x57 */
    u8 IPR28;		/* DMA + 0x58 */
    u8 IPR29;		/* DMA + 0x59 */
    u8 IPR30;		/* DMA + 0x5a */
    u8 IPR31;		/* DMA + 0x5b */

    u32 res1;		/* DMA + 0x5c */
    u32 res2;		/* DMA + 0x60 */
    u32 res3;		/* DMA + 0x64 */
    u32 MDEDebug;	/* DMA + 0x68 */
    u32 ADSDebug;	/* DMA + 0x6c */
    u32 Value1;		/* DMA + 0x70 */
    u32 Value2;		/* DMA + 0x74 */
    u32 Control;	/* DMA + 0x78 */
    u32 Status;		/* DMA + 0x7c */
    u32 EU00;		/* DMA + 0x80 */
    u32 EU01;		/* DMA + 0x84 */
    u32 EU02;		/* DMA + 0x88 */
    u32 EU03;		/* DMA + 0x8c */
    u32 EU04;		/* DMA + 0x90 */
    u32 EU05;		/* DMA + 0x94 */
    u32 EU06;		/* DMA + 0x98 */
    u32 EU07;		/* DMA + 0x9c */
    u32 EU10;		/* DMA + 0xa0 */
    u32 EU11;		/* DMA + 0xa4 */
    u32 EU12;		/* DMA + 0xa8 */
    u32 EU13;		/* DMA + 0xac */
    u32 EU14;		/* DMA + 0xb0 */
    u32 EU15;		/* DMA + 0xb4 */
    u32 EU16;		/* DMA + 0xb8 */
    u32 EU17;		/* DMA + 0xbc */
    u32 EU20;		/* DMA + 0xc0 */
    u32 EU21;		/* DMA + 0xc4 */
    u32 EU22;		/* DMA + 0xc8 */
    u32 EU23;		/* DMA + 0xcc */
    u32 EU24;		/* DMA + 0xd0 */
    u32 EU25;		/* DMA + 0xd4 */
    u32 EU26;		/* DMA + 0xd8 */
    u32 EU27;		/* DMA + 0xdc */
    u32 EU30;		/* DMA + 0xe0 */
    u32 EU31;		/* DMA + 0xe4 */
    u32 EU32;		/* DMA + 0xe8 */
    u32 EU33;		/* DMA + 0xec */
    u32 EU34;		/* DMA + 0xf0 */
    u32 EU35;		/* DMA + 0xf4 */
    u32 EU36;		/* DMA + 0xf8 */
    u32 EU37;		/* DMA + 0xfc */
};


/* function prototypes */
void loadtask(int basetask, int tasks);
u32 dramSetup(void);

#if defined(CONFIG_PSC_CONSOLE)
int psc_serial_init (void);
void psc_serial_putc(const char c);
void psc_serial_puts (const char *s);
int psc_serial_getc(void);
int psc_serial_tstc(void);
void psc_serial_setbrg(void);
#endif

#if defined (CONFIG_EXTUART_CONSOLE)
int ext_serial_init (void);
void ext_serial_putc(const char c);
void ext_serial_puts (const char *s);
int ext_serial_getc(void);
int ext_serial_tstc(void);
void ext_serial_setbrg(void);
#endif

#endif /* __ASSEMBLY__ */

#endif /* __MPC8220_H__ */