mpc8220.h

F:worksip2440a board可启动u-boot-like.tar.gz F:worksip2440a board可启动u-boot-like.tar.gz

/*
 * include/mpc8220.h
 *
 * Prototypes, etc. for the Motorola MPC8220
 * embedded cpu chips
 *
 * 2004 (c) Freescale, Inc.
 * Author: TsiChung Liew <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __MPC8220_H__
#define __MPC8220_H__

/* Processor name */
#if defined(CONFIG_MPC8220)
#define CPU_ID_STR	    "MPC8220"
#endif

/* Exception offsets (PowerPC standard) */
#define EXC_OFF_SYS_RESET   0x0100

/* Internal memory map */
/* MPC8220 Internal Register MMAP */
#define MMAP_MBAR	(CFG_MBAR + 0x00000000) /* chip selects		     */
#define MMAP_MEMCTL	(CFG_MBAR + 0x00000100) /* sdram controller	     */
#define MMAP_XLBARB	(CFG_MBAR + 0x00000200) /* xlb arbitration control   */
#define MMAP_CDM	(CFG_MBAR + 0x00000300) /* clock distribution module */
#define MMAP_VDOPLL	(CFG_MBAR + 0x00000400) /* video PLL		     */
#define MMAP_FB		(CFG_MBAR + 0x00000500) /* flex bus controller	     */
#define MMAP_PCFG	(CFG_MBAR + 0x00000600) /* port config		     */
#define MMAP_ICTL	(CFG_MBAR + 0x00000700) /* interrupt controller	     */
#define MMAP_GPTMR	(CFG_MBAR + 0x00000800) /* general purpose timers    */
#define MMAP_SLTMR	(CFG_MBAR + 0x00000900) /* slice timers		     */
#define MMAP_GPIO	(CFG_MBAR + 0x00000A00) /* gpio module		     */
#define MMAP_XCPCI	(CFG_MBAR + 0x00000B00) /* pci controller	     */
#define MMAP_PCIARB	(CFG_MBAR + 0x00000C00) /* pci arbiter		     */
#define MMAP_EXTDMA1	(CFG_MBAR + 0x00000D00) /* external dma1	     */
#define MMAP_EXTDMA2	(CFG_MBAR + 0x00000E00) /* external dma1	     */
#define MMAP_USBH	(CFG_MBAR + 0x00001000) /* usb host		     */
#define MMAP_CMTMR	(CFG_MBAR + 0x00007f00) /* comm timers		     */
#define MMAP_DMA	(CFG_MBAR + 0x00008000) /* dma			     */
#define MMAP_USBD	(CFG_MBAR + 0x00008200) /* usb device		     */
#define MMAP_COMMPCI	(CFG_MBAR + 0x00008400) /* pci comm Bus regs	     */
#define MMAP_1284	(CFG_MBAR + 0x00008500) /* 1284			     */
#define MMAP_PEV	(CFG_MBAR + 0x00008600) /* print engine video	     */
#define MMAP_PSC1	(CFG_MBAR + 0x00008800) /* psc1 block		     */
#define MMAP_I2C	(CFG_MBAR + 0x00008f00) /* i2c controller	     */
#define MMAP_FEC1	(CFG_MBAR + 0x00009000) /* fast ethernet 1	     */
#define MMAP_FEC2	(CFG_MBAR + 0x00009800) /* fast ethernet 2	     */
#define MMAP_JBIGRAM	(CFG_MBAR + 0x0000a000) /* jbig RAM		     */
#define MMAP_JBIG	(CFG_MBAR + 0x0000c000) /* jbig			     */
#define MMAP_PDLA	(CFG_MBAR + 0x00010000) /*			     */
#define MMAP_SRAMCFG	(CFG_MBAR + 0x0001ff00) /* SRAM config		     */
#define MMAP_SRAM	(CFG_MBAR + 0x00020000) /* SRAM			     */

#define SRAM_SIZE	0x8000			/* 32 KB */

/* ------------------------------------------------------------------------ */
/*
 * Macro for Programmable Serial Channel
 */
/* equates for mode reg. 1 for channel	A or B */
#define PSC_MR1_RX_RTS		0x80000000    /* receiver RTS enabled */
#define PSC_MR1_RX_INT		0x40000000    /* receiver intrupt enabled */
#define PSC_MR1_ERR_MODE	0x20000000    /* block error mode */
#define PSC_MR1_PAR_MODE_MULTI	0x18000000    /* multi_drop mode */
#define PSC_MR1_NO_PARITY	0x10000000    /* no parity mode */
#define PSC_MR1_ALWAYS_0	0x08000000    /* force parity mode */
#define PSC_MR1_ALWAYS_1	0x0c000000    /* force parity mode */
#define PSC_MR1_EVEN_PARITY	0x00000000    /* parity mode */
#define PSC_MR1_ODD_PARITY	0x04000000    /* 0 = even, 1 = odd */
#define PSC_MR1_BITS_CHAR_8	0x03000000    /* 8 bits */
#define PSC_MR1_BITS_CHAR_7	0x02000000    /* 7 bits */
#define PSC_MR1_BITS_CHAR_6	0x01000000    /* 6 bits */
#define PSC_MR1_BITS_CHAR_5	0x00000000    /* 5 bits */

/* equates for mode reg. 2 for channel	A or B */
#define PSC_MR2_NORMAL_MODE	0x00000000    /* normal channel mode */
#define PSC_MR2_AUTO_MODE	0x40000000    /* automatic channel mode */
#define PSC_MR2_LOOPBACK_LOCL	0x80000000    /* local loopback channel mode */
#define PSC_MR2_LOOPBACK_REMT	0xc0000000    /* remote loopback channel mode */
#define PSC_MR2_TX_RTS		0x20000000    /* transmitter RTS enabled */
#define PSC_MR2_TX_CTS		0x10000000    /* transmitter CTS enabled */
#define PSC_MR2_STOP_BITS_2	0x0f000000    /* 2 stop bits */
#define PSC_MR2_STOP_BITS_1	0x07000000    /* 1 stop bit */

/* equates for status reg. A or B */
#define PSC_SR_BREAK		0x80000000    /* received break */
#define PSC_SR_NEOF		PSC_SR_BREAK  /* Next byte is EOF - MIR/FIR */
#define PSC_SR_FRAMING		0x40000000    /* framing error */
#define PSC_SR_PHYERR		PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */
#define PSC_SR_PARITY		0x20000000    /* parity error */
#define PSC_SR_CRCERR		PSC_SR_PARITY /* CRC error */
#define PSC_SR_OVERRUN		0x10000000    /* overrun error */
#define PSC_SR_TXEMT		0x08000000    /* transmitter empty */
#define PSC_SR_TXRDY		0x04000000    /* transmitter ready*/
#define PSC_SR_FFULL		0x02000000    /* fifo full */
#define PSC_SR_RXRDY		0x01000000    /* receiver ready */
#define PSC_SR_DEOF		0x00800000    /* Detect EOF or RX-FIFO contain EOF */
#define PSC_SR_ERR		0x00400000    /* Error Status including FIFO */

/* equates for clock select reg. */
#define PSC_CSRX16EXT_CLK	0x1110	/* x 16 ext_clock */
#define PSC_CSRX1EXT_CLK	0x1111	/* x 1 ext_clock  */

/* equates for command reg. A or B */
#define PSC_CR_NO_COMMAND	0x00000000    /* no command */
#define PSC_CR_RST_MR_PTR_CMD	0x10000000    /* reset mr pointer command */
#define PSC_CR_RST_RX_CMD	0x20000000    /* reset receiver command */
#define PSC_CR_RST_TX_CMD	0x30000000    /* reset transmitter command */
#define PSC_CR_RST_ERR_STS_CMD	0x40000000    /* reset error status cmnd */
#define PSC_CR_RST_BRK_INT_CMD	0x50000000    /* reset break int. command */
#define PSC_CR_STR_BREAK_CMD	0x60000000    /* start break command */
#define PSC_CR_STP_BREAK_CMD	0x70000000    /* stop break command */
#define PSC_CR_RX_ENABLE	0x01000000    /* receiver enabled */
#define PSC_CR_RX_DISABLE	0x02000000    /* receiver disabled */
#define PSC_CR_TX_ENABLE	0x04000000    /* transmitter enabled */
#define PSC_CR_TX_DISABLE	0x08000000    /* transmitter disabled */

/* equates for input port change reg. */
#define PSC_IPCR_SYNC		0x80000000    /* Sync Detect */
#define PSC_IPCR_D_CTS		0x10000000    /* Delta CTS */
#define PSC_IPCR_CTS		0x01000000    /* CTS - current state of PSC_CTS */

/* equates for auxiliary control reg. (timer and counter clock selects) */
#define PSC_ACR_BRG		0x80000000    /* for 68681 compatibility
						 baud rate gen select
						 0 = set 1; 1 = set 2
						 equates are set 2 ONLY */
#define PSC_ACR_TMR_EXT_CLK_16	0x70000000    /* xtnl clock divided by 16 */
#define PSC_ACR_TMR_EXT_CLK	0x60000000    /* external clock */
#define PSC_ACR_TMR_IP2_16	0x50000000    /* ip2 divided by 16 */
#define PSC_ACR_TMR_IP2		0x40000000    /* ip2 */
#define PSC_ACR_CTR_EXT_CLK_16	0x30000000    /* xtnl clock divided by 16 */
#define PSC_ACR_CTR_TXCB	0x20000000    /* channel B xmitr clock */
#define PSC_ACR_CTR_TXCA	0x10000000    /* channel A xmitr clock */
#define PSC_ACR_CTR_IP2		0x00000000    /* ip2 */
#define PSC_ACR_IEC0		0x01000000    /* interrupt enable ctrl for D_CTS */

/* equates for int. status reg. */
#define PSC_ISR_IPC		0x80000000    /* input port change*/
#define PSC_ISR_BREAK		0x04000000    /* delta break */
#define PSC_ISR_RX_RDY		0x02000000    /* receiver rdy /fifo full */
#define PSC_ISR_TX_RDY		0x01000000    /* transmitter ready */
#define PSC_ISR_DEOF		0x00800000    /* Detect EOF / RX-FIFO contains EOF */
#define PSC_ISR_ERR		0x00400000    /* Error Status including FIFO */

/* equates for int. mask reg. */
#define PSC_IMR_CLEAR		0xff000000    /* Clear the imr */
#define PSC_IMR_IPC		0x80000000    /* input port change*/
#define PSC_IMR_BREAK		0x04000000    /* delta break */
#define PSC_IMR_RX_RDY		0x02000000    /* rcvr ready / fifo full */
#define PSC_IMR_TX_RDY		0x01000000    /* transmitter ready */
#define PSC_IMR_DEOF		0x00800000    /* Detect EOF / RX-FIFO contains EOF */
#define PSC_IMR_ERR		0x00400000    /* Error Status including FIFO */

/* equates for input port reg. */
#define PSC_IP_LPWRB		0x80000000    /* Low power mode in Ac97 */
#define PSC_IP_TGL		0x40000000    /* test usage */
#define PSC_IP_CTS		0x01000000    /* CTS */

/* equates for output port bit set reg. */
#define PSC_OPSET_RTS		0x01000000    /* Assert PSC_RTS output */

/* equates for output port bit reset reg. */
#define PSC_OPRESET_RTS		0x01000000    /* Assert PSC_RTS output */

/* equates for rx FIFO number of data reg. */
#define PSC_RFNUM(x)		((x&0xff)<<24)/* receive count */

/* equates for tx FIFO number of data reg. */
#define PSC_TFNUM(x)		((x&0xff)<<24)/* receive count */

/* equates for rx FIFO status reg */
#define PSC_RFSTAT_TAG(x)	((x&3)<<28)   /* tag */
#define PSC_RFSTAT_FRAME0	0x08	      /* Frame Indicator 0 */
#define PSC_RFSTAT_FRAME1	0x04	      /* Frame Indicator 1 */
#define PSC_RFSTAT_FRAME2	0x02	      /* Frame Indicator 2 */
#define PSC_RFSTAT_FRAME3	0x01	      /* Frame Indicator 3 */
#define PSC_RFSTAT_FRAME(x)	((x&0x0f)<<24)/* Frame indicator */
#define PSC_RFSTAT_ERR		0x00400000    /* Fifo err */
#define PSC_RFSTAT_UF		0x00200000    /* Underflow */
#define PSC_RFSTAT_OF		0x00100000    /* overflow */
#define PSC_RFSTAT_FR		0x00080000    /* frame ready */
#define PSC_RFSTAT_FULL		0x00040000    /* full */
#define PSC_RFSTAT_ALARM	0x00020000    /* alarm */
#define PSC_RFSTAT_EMPTY	0x00010000    /* empty */

/* equates for tx FIFO status reg */
#define PSC_TFSTAT_TAG(x)	((x&3)<<28)   /* tag */
#define PSC_TFSTAT_FRAME0	0x08	      /* Frame Indicator 0 */
#define PSC_TFSTAT_FRAME1	0x04	      /* Frame Indicator 1 */
#define PSC_TFSTAT_FRAME2	0x02	      /* Frame Indicator 2 */
#define PSC_TFSTAT_FRAME3	0x01	      /* Frame Indicator 3 */
#define PSC_TFSTAT_FRAME(x)	((x&0x0f)<<24)/* Frame indicator */
#define PSC_TFSTAT_ERR		0x00400000    /* Fifo err */
#define PSC_TFSTAT_UF		0x00200000    /* Underflow */
#define PSC_TFSTAT_OF		0x00100000    /* overflow */
#define PSC_TFSTAT_FR		0x00080000    /* frame ready */
#define PSC_TFSTAT_FULL		0x00040000    /* full */
#define PSC_TFSTAT_ALARM	0x00020000    /* alarm */
#define PSC_TFSTAT_EMPTY	0x00010000    /* empty */

/* equates for rx FIFO control reg. */
#define PSC_RFCNTL_WTAG(x)	((x&3)<<29)   /* Write tag */
#define PSC_RFCNTL_FRAME	0x08000000    /* Frame mode enable */
#define PSC_RFCNTL_GR(x)	((x&7)<<24)   /* Granularity */

/* equates for tx FIFO control reg. */
#define PSC_TFCNTL_WTAG(x)	((x&3)<<29)   /* Write tag */
#define PSC_TFCNTL_FRAME	0x08000000    /* Frame mode enable */
#define PSC_TFCNTL_GR(x)	((x&7)<<24)   /* Granularity */

/* equates for rx FIFO alarm reg */
#define PSC_RFALARM(x)		(x&0x1ff)     /* Alarm */

/* equates for tx FIFO alarm reg */
#define PSC_TFALARM(x)		(x&0x1ff)     /* Alarm */

/* equates for rx FIFO read pointer */
#define PSC_RFRPTR(x)		(x&0x1ff)     /* read pointer */

/* equates for tx FIFO read pointer */
#define PSC_TFRPTR(x)		(x&0x1ff)     /* read pointer */

/* equates for rx FIFO write pointer */
#define PSC_RFWPTR(x)		(x&0x1ff)     /* write pointer */

/* equates for rx FIFO write pointer */
#define PSC_TFWPTR(x)		(x&0x1ff)     /* write pointer */

/* equates for rx FIFO last read frame pointer reg */
#define PSC_RFLRFPTR(x)		(x&0x1ff)     /* last read frame pointer */

/* equates for tx FIFO last read frame pointer reg */
#define PSC_TFLRFPTR(x)		(x&0x1ff)     /* last read frame pointer */

/* equates for rx FIFO last write frame pointer reg */
#define PSC_RFLWFPTR(x)		(x&0x1ff)     /* last write frame pointer */

/* equates for tx FIFO last write frame pointer reg */
#define PSC_TFLWFPTR(x)		(x&0x1ff)     /* last write frame pointer */


/* ------------------------------------------------------------------------ */
/*
 * Macro for General Purpose Timer
 */
/* Enable and Mode Select */
#define GPT_OCT(x)	    (x & 0x3)<<4/* Output Compare Type */
#define GPT_ICT(x)	    (x & 0x3)	/* Input Capture Type */
#define GPT_CTRL_WDEN	    0x80	/* Watchdog Enable */
#define GPT_CTRL_CE	    0x10	/* Counter Enable */
#define GPT_CTRL_STPCNT	    0x04	/* Stop continous */
#define GPT_CTRL_ODRAIN	    0x02	/* Open Drain */
#define GPT_CTRL_INTEN	    0x01	/* Interrupt Enable */
#define GPT_MODE_GPIO(x)    (x & 0x3)<<4/* Gpio Mode Type */
#define GPT_TMS_ICT	    0x01	/* Input Capture Enable */
#define GPT_TMS_OCT	    0x02	/* Output Capture Enable */