aesop2440.h

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/*
 * (C) Copyright 2002
 * Kernelproject.org <www.kernelproject.org>
 * Junyoung Song <[e-mail]>
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <[e-mail]>
 * Gary Jennejohn <[e-mail]>
 * David Mueller <[e-mail]>
 *
 * Configuation settings for the SAMSUNG SMDK2410 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * If we are developing, we might want to start armboot from ram
 * so we MUST NOT initialize critical regs like mem-timing ...
 */
//#define CONFIG_INIT_CRITICAL		/* undef for developing */
#define CONFIG_INIT_CRITICAL
/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
#define	CONFIG_S3C2440		1	/* in a SAMSUNG S3C2440 SoC     */
#define CONFIG_AESOP2440	1	/* on a Kernelproject aESOP2440 Board  */

/* input clock of PLL */
#if 1
#define CONFIG_SYS_CLK_FREQ	16934400/* the SMDK2410 has 12MHz input clock */
#else
#define CONFIG_SYS_CLK_FREQ	12000000/* the SMDK2410 has 12MHz input clock */
#endif

#define USE_920T_MMU		1
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

#undef CONFIG_BZ2_LOGO
#ifdef CONFIG_BZ2_LOGO
/* BZIP2 support */
#define CONFIG_BZIP2			/* for BZ2-type aESOP logo image */
#endif

/*
 * Size of malloc() pool
 */
#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 4*1024*1024)
#else
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
#endif
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/* Board Late Init */
#define BOARD_LATE_INIT

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_DM9000	1	/* we have a CS8900 on-board */
#define DM9000_BASE		0x18000000
#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1          0	/* we use SERIAL 1 on aESOP2440 */

/************************************************************
 * aESOP2440 LCD
 ************************************************************/
//#define CONFIG_AESOP_LCD	1
//#define CONFIG_CFB_CONSOLE	 /*ÉèÖÃFB*/
//#define CONFIG_VIDEO_SM501		  /*ÉèÖÃFBµÄÏÔ¿šÇý¶¯*/
/*************ÏÔ¿šµØÖ·***********************/
//#define CONFIG_SM501_MEM_BASE     0x8000000
//#define CONFIG_SM501_REG_BASE     0x8000000+0x3e00000
/*******************************************/
//#define CONFIG_VIDEO_LOGO
//#define CONFIG_BMP_LOGO

#if 0
	#define AESOP_FB_BASE		0x33800000	/* frame buffer address */
#else
	#define AESOP_FB_BASE		0x33000000	/* frame buffer address, ghcstop fix */
#endif	

/************************************************************
 * RTC
 ************************************************************/
#define	CONFIG_RTC_S3C24X0	1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		115200


#define CONFIG_MMC 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SUPPORT_VFAT 1

/***********************************************************
 * Command definition
 ***********************************************************/
#define CONFIG_COMMANDS \
			(CONFIG_CMD_DFL	 | \
			CFG_CMD_CACHE	 | \
			CFG_CMD_NAND	 | \
                        CFG_CMD_FLASH    | \
			/*CFG_CMD_EEPROM |*/ \
			/*CFG_CMD_I2C	 |*/ \
			/*CFG_CMD_USB	 |*/ \
			/*CFG_CMD_SM501 |*/\
			CFG_CMD_FAT      | \
			/*CFG_CMD_SD       |*/ \
			CFG_CMD_MMC      | \
			CFG_CMD_REGINFO  | \
			CFG_CMD_DATE	 | \
			CFG_CMD_BSP	 | \
			CFG_CMD_ELF)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_BOOTDELAY	1
/*#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600" */
#define CONFIG_ETHADDR		08:00:3e:26:0a:5b 
#define CONFIG_NETMASK          255.255.255.0
#define CONFIG_IPADDR		200.200.200.190
#define CONFIG_SERVERIP		200.200.200.138
#define CONFIG_GATEWAYIP	200.200.200.77
/*#define CONFIG_BOOTFILE	"elinos-lart" */
/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */

/* jeenspa fix - nand boot */
#if 0
/* ghcstop fix */
#define CONFIG_BOOTCOMMAND	"tftp 32000000 aesopk;bootm 32000000"
#else
#define CONFIG_BOOTCOMMAND	"nand read 32000000 0 200000;bootm 32000000"
#endif

/*
 * ghcstop add
 * NFS setting howto
 * root=/dev/nfs rw nfsroot=[host ip]:[nfs root directory] ip=[target ip]:[host ip]:[gw ip]:[netmask]:[hostname]:[device]:[autoconfiguration]
 * 
 * ethaddr is for automatic ethernet address setting used in drivers/net/cs89x0.c
 *(needs kernel driver code fix)
 */
//#if UBOOT_FOR_LINUX_2420 
#if 1 /* 2.4.x kernel */
	//#define CONFIG_BOOTARGS     "root=/dev/nfs rw nfsroot=200.200.200.138:/root/mmsp2nfs ip=200.200.200.190:200.200.200.138:200.200.200.77:255.255.255.0::eth0:off ethaddr=08:00:3e:26:0a:5b"
/* jeenspa fix - nand boot */
#define CONFIG_BOOTARGS	"root=/dev/mtdblock1 ip=192.168.10.21:192.168.10.10:192.168.10.1:255.255.255.0::eth0:off ethaddr=11:22:33:44:55:66 noinitrd console=ttyS0"
	//#define CONFIG_BOOTARGS     "root=/dev/nfs rw nfsroot=192.168.10.10:/korea-dokdo/nfsmount/rootfs-aesop ip=192.168.10.21:192.168.10.10:192.168.10.1:255.255.255.0::eth0:off ethaddr=08:00:3e:26:0a:5b"
	//#define CONFIG_BOOTARGS     "root=/dev/nfs rw nfsroot=192.168.10.10:/root/mmsp2nfs ip=192.168.10.4:192.168.10.10:192.168.10.1:255.255.255.0::eth0:off ethaddr=08:00:3e:26:0a:5b"
#else /* 2.6.x kernel */
/* jeenspa fix - nand boot */
#define CONFIG_BOOTARGS	"root=/dev/mtdblock1 ip=192.168.10.21:192.168.10.10:192.168.10.1:255.255.255.0::eth0:off ethaddr=11:22:33:44:55:66 noinitrd console=ttySAC0,115200n81"
	//#define CONFIG_BOOTARGS     "root=/dev/nfs rw nfsroot=192.168.10.10:/korea-dokdo/nfsmount/rootfs-aesop ip=192.168.10.21:192.168.10.10:192.168.10.1:255.255.255.0::eth0:off console=ttySAC0,115200n81 ethaddr=08:00:3e:26:0a:5b"
#endif	


#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP				/* undef to save memory		*/
#define	CFG_PROMPT		"Teach2440 # "	/* Monitor Command Prompt	*/
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/

#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define	CFG_LOAD_ADDR		0x32000000	/* default load address	*/

/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
/* it to wrap 100 times (total 1562500) to get 1 sec. */
#define	CFG_HZ			1562500

/* valid baudrates */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */

//like//
#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */

 #define PHYS_FLASH_SIZE        0x01000000 /* 16 MB */
 #define CFG_FLASH_PROTECTION
#define CFG_FLASH_BASE		PHYS_FLASH_1

 #define CFG_MONITOR_BASE  PHYS_FLASH_1
/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */


#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */


#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */

#define CFG_FLASH_ERASE_TOUT   (16*CFG_HZ) /* Timeout for Flash Erase */

#define CFG_FLASH_WRITE_TOUT  (16*CFG_HZ) /* Timeout for Flash Write */

#define    CFG_ENV_IS_IN_FLASH    1

#define CFG_ENV_ADDR           (PHYS_FLASH_1 + 0x40000)

#define CFG_ENV_SIZE       0x20000  /* Total Size of Environment Sector     */


#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */


/*-----------------------------------------------------------------------
 * NAND FLASH organization
 */
#define CONFIG_AESOP_YAFFS
#define CFG_MAX_NAND_DEVICE 1
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 3
#define ADDR_COLUMN_PAGE 4
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_WAIT_READY(nand)		udelay(10); while(!(rNFSTAT & 0x01))
#define WRITE_NAND_COMMAND(d, adr)	rNFCMD = d
#define WRITE_NAND_ADDRESS(d, adr)	rNFADDR = d
#define WRITE_NAND(d, adr)		rNFDATA = d
#define READ_NAND(adr)			rNFDATA
#define NAND_DISABLE_CE(nand)		rNFCONT |= 0x02
#define NAND_ENABLE_CE(nand)		rNFCONT &= ~(0x02)
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)

/*-----------------------------------------------------------------------
 * aESOP USB Device Mass-storage support
 */
#define CONFIG_AESOP_USBDMASS
/*-------------------------------------------------------------------------*/


/* ghcstop: tag setting is transfered to kernel */
#if 1
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG 
#endif

#endif	/* __CONFIG_H */