readme.alaska8220

F:worksip2440a board可启动u-boot-like.tar.gz F:worksip2440a board可启动u-boot-like.tar.gz

Freescale Alaska MPC8220 board
==============================

TsiChung Liew([e-mail])
Created 9/21/04
===========================================


Changed files:
==============

- Makefile		    added MPC8220 and Alaska8220_config
- MAKEALL		    added MPC8220 and Alaska8220
- README		    added CONFIG_MPC8220, Alaska8220_config

- common/cmd_bdinfo.c	    added board information members for MPC8220
- common/cmd_bootm.c	    added clocks for MPC8220 in do_bootm_linux()

- include/common.h	    added CONFIG_MPC8220

- include/asm-ppc/u-boot.h  added board information members for MPC8220
- include/asm-ppc/global_data.h added global variables - inp_clk, pci_clk,
			    vco_clk, pev_clk, flb_clk, and bExtUart

- lib_ppc/board.c	    added CONFIG_MPC8220 support

- net/eth.c		    added FEC support for MPC8220

Added files:
============
- board/alaska		    directory for Alaska MPC8220
- board/alaska/alaska.c	    Alaska dram and BATs setup
- board/alaska/extserial.c  external serial (debug card serial) support
- board/alaska/flash.c	    Socket (AMD) and Onboard (INTEL) flash support
- board/alaska/serial.c	    to determine which int/ext serial to use
- board/alaska/Makefile	    Makefile
- board/alaska/config.mk    config make
- board/alaska/u-boot.lds   Linker description

- cpu/mpc8220/dma.h	    multi-channel dma header file
- cpu/mpc8220/dramSetup.h   dram setup header file
- cpu/mpc8220/fec.h	    MPC8220 FEC header file
- cpu/mpc8220/cpu.c	    cpu specific code
- cpu/mpc8220/cpu_init.c    Flexbus ChipSelect and Mux pins setup
- cpu/mpc8220/dramSetup.c   MPC8220 DDR SDRAM setup
- cpu/mpc8220/fec.c	    MPC8220 FEC driver
- cpu/mpc8220/i2c.c	    MPC8220 I2C driver
- cpu/mpc8220/interrupts.c  interrupt support (not enable)
- cpu/mpc8220/loadtask.c    load dma
- cpu/mpc8220/speed.c	    system, pci, flexbus, pev, and cpu clock
- cpu/mpc8220/traps.c	    exception
- cpu/mpc8220/uart.c	    MPC8220 UART driver
- cpu/mpc8220/Makefile	    Makefile
- cpu/mpc8220/config.mk	    config make
- cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
- cpu/mpc8220/io.S	    io functions
- cpu/mpc8220/start.S	    start up

- include/mpc8220.h

- include/asm-ppc/immap_8220.h

- include/configs/Alaska8220.h


1. SWITCH SETTINGS
==================
1.1 SW1: 0 - Boot from Socket Flash (AMD) or 1 - Onboard Flash (INTEL)
    SW2: 0 - Select MPC8220 UART or 1 - Debug Card UART
    SW3: unsed
    SW4: 0 - 1284 or 1 - FEC1
    SW5: 0 - PEV or 1 - FEC2


2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
     linux kernel, you can customize it based on your system requirements:
      DDR:	    0x00000000-0x1fffffff (max 512MB)
      MBAR:	    0xf0000000-0xf0027fff (128KB)
      CPLD:	    0xf1000000-0xf103ffff (256KB)
      FPGA:	    0xf2000000-0xf203ffff (256KB)
      Flash:	    0xfe000000-0xffffffff (max 32MB)

3. DEFINITIONS AND COMPILATION
==============================
3.1 Explanation on NEW definitions in include/configs/alaska8220.h
    CONFIG_MPC8220	    MPC8220 specific
    CONFIG_ALASKA8220	    Alaska board specific
    CFG_MPC8220_CLKIN	    Define Alaska Input Clock
    CONFIG_PSC_CONSOLE	    Enable MPC8220 UART
    CONFIG_EXTUART_CONSOLE  Enable External 16552 UART
    CFG_AMD_BOOT	    To determine the u-boot is booted from AMD or Intel
    CFG_MBAR		    MBAR base address
    CFG_DEFAULT_MBAR	    Reset MBAR base address

3.2 Compilation
   export CROSS_COMPILE=cross-compile-prefix
   cd u-boot-1-1-x
   make distclean
   make Alaska8220_config
   make


4. SCREEN DUMP
==============
4.1 Alaska MPC8220 board
    Boot from AMD (NOTE: May not show exactly the same)

U-Boot 1.1.1 (Sep 22 2004 - 22:14:41)

CPU:   MPC8220 (JTAG ID 1640301d) at 300 MHz
       Bus 120 MHz, CPU 300 MHz, PCI 30 MHz, VCO 480 MHz
Board: Alaska MPC8220 Evaluation Board
I2C:   93 kHz, ready
DRAM:  256 MB
Reserving 167k for U-Boot at: 0ffd6000
FLASH: 16.5 MB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC ETHERNET
=> flinfo

Bank # 1: INTEL 28F128J3A
  Size: 8 MB in 64 Sectors
  Sector Start Addresses:
    FE000000	  FE020000	FE040000      FE060000	    FE080000
    FE0A0000	  FE0C0000	FE0E0000      FE100000	    FE120000
    FE140000	  FE160000	FE180000      FE1A0000	    FE1C0000
    FE1E0000	  FE200000	FE220000      FE240000	    FE260000
    FE280000	  FE2A0000	FE2C0000      FE2E0000	    FE300000
    FE320000	  FE340000	FE360000      FE380000	    FE3A0000
    FE3C0000	  FE3E0000	FE400000      FE420000	    FE440000
    FE460000	  FE480000	FE4A0000      FE4C0000	    FE4E0000
    FE500000	  FE520000	FE540000      FE560000	    FE580000
    FE5A0000	  FE5C0000	FE5E0000      FE600000	    FE620000
    FE640000	  FE660000	FE680000      FE6A0000	    FE6C0000
    FE6E0000	  FE700000	FE720000      FE740000	    FE760000
    FE780000	  FE7A0000	FE7C0000      FE7E0000

Bank # 2: INTEL 28F128J3A
  Size: 8 MB in 64 Sectors
  Sector Start Addresses:
    FE800000	  FE820000	FE840000      FE860000	    FE880000
    FE8A0000	  FE8C0000	FE8E0000      FE900000	    FE920000
    FE940000	  FE960000	FE980000      FE9A0000	    FE9C0000
    FE9E0000	  FEA00000	FEA20000      FEA40000	    FEA60000
    FEA80000	  FEAA0000	FEAC0000      FEAE0000	    FEB00000
    FEB20000	  FEB40000	FEB60000      FEB80000	    FEBA0000
    FEBC0000	  FEBE0000	FEC00000      FEC20000	    FEC40000
    FEC60000	  FEC80000	FECA0000      FECC0000	    FECE0000
    FED00000	  FED20000	FED40000      FED60000	    FED80000
    FEDA0000	  FEDC0000	FEDE0000      FEE00000	    FEE20000
    FEE40000	  FEE60000	FEE80000      FEEA0000	    FEEC0000
    FEEE0000	  FEF00000 (RO) FEF20000 (RO) FEF40000	    FEF60000
    FEF80000	  FEFA0000	FEFC0000      FEFE0000 (RO)

Bank # 3: AMD AMD29F040B
  Size: 0 MB in 7 Sectors
  Sector Start Addresses:
    FFF00000 (RO) FFF10000 (RO) FFF20000 (RO) FFF30000	    FFF40000
    FFF50000	  FFF60000

Bank # 4: AMD AMD29F040B
  Size: 0 MB in 1 Sectors
  Sector Start Addresses:
    FFF70000 (RO)
=> bdinfo

memstart    = 0xF0009800
memsize	    = 0x10000000
flashstart  = 0xFFF00000
flashsize   = 0x01080000
flashoffset = 0x00025000
sramstart   = 0xF0020000
sramsize    = 0x00008000
bootflags   = 0x00000001
intfreq	    =	 300 MHz
busfreq	    =	 120 MHz
inpfreq	    =	  30 MHz
flbfreq	    =	  30 MHz
pcifreq	    =	  30 MHz
vcofreq	    =	 480 MHz
pevfreq	    =	  81 MHz
ethaddr	    = 00:E0:0C:BC:E0:60
eth1addr    = 00:E0:0C:BC:E0:61
IP addr	    = 192.162.1.2
baudrate    = 115200 bps
=> printenv
bootargs=root=/dev/ram rw
bootdelay=5
baudrate=115200
ethaddr=00:e0:0c:bc:e0:60
eth1addr=00:e0:0c:bc:e0:61
ipaddr=192.162.1.2
serverip=192.162.1.1
gatewayip=192.162.1.1
netmask=255.255.255.0
hostname=Alaska
stdin=serial
stdout=serial
stderr=serial
ethact=FEC ETHERNET

Environment size: 268/65532 bytes
=> setenv ipaddr 192.160.1.2
=> setenv serverip 192.160.1.1
=> setenv gatewayip 192.160.1.1
=> saveenv
Saving Environment to Flash...

.
Un-Protected 1 sectors
Erasing Flash...
Erasing sector	0 ...  done
Erased 1 sectors
Writing to Flash... done

.
Protected 1 sectors
=> tftp 0x10000 linux.elf
Using FEC ETHERNET device
TFTP from server 192.160.1.1; our IP address is 192.160.1.2; sending through gateway 192.160.1.1
Filename 'linux.elf'.
Load address: 0x10000
Loading: invalid RARP header
#################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 ##################################################
done
Bytes transferred = 2917494 (2c8476 hex)
=> bootelf
Loading .text @ 0x00a00000 (23820 bytes)