readme.rpxlite

F:worksip2440a board可启动u-boot-like.tar.gz F:worksip2440a board可启动u-boot-like.tar.gz

	=> 0xFE00 0140

/*### BR1 & OR1 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */
/*### SDRAM */

	BA   = 0000 0000 0000 0000 0	/* Base addr = 0x0000 0000 */
	AT   = 000
	PS   = 00
	PARE = 0
	WP   = 0
	MS   = 1 				/* UPMA */
	V    = 1				/* Valid */

	=> 0x0000 0081

	AM            = 1111 1110 0000 0000	/* 32MBytes */
	ATM           = 000
	CSNT/SAM      = 1
	ACS/G5LA,G5LS = 11
	BIH           = 0
	SCY           = 0000		/* cycle length = 0 */
	SETA          = 0
	TRLX          = 0
	EHTR          = 0

	=> 0xFE00 0E00

/*### BR2 & OR2 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */

	BR2 & OR2 = 0x0000 0000		/* Not used */

/*### BR3 & OR3 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */
/*### BCSR */

	BA   = 1111 1010 0100 0000 0	/* Base addr = 0xFA40 0000 */
	AT   = 000
	PS   = 00
	PARE = 0
	WP   = 0
	MS   = 0 				/* GPCM */
	V    = 1				/* Valid */

	=> 0xFA40 0001

	AM            = 1111 1111 0111 1111 1	/* (?) */
	ATM           = 000
	CSNT/SAM      = 1
	ACS/G5LA,G5LS = 00
	BIH           = 1			/* Burst inhibited */
	SCY           = 0001		/* cycle length = 1 */
	SETA          = 0
	TRLX          = 0

	=> 0xFF7F 8910

/*### BR4 & OR4 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */
/*### NVRAM & SRAM */

	BA   = 1111 1010 0000 0000 0	/* Base addr = 0xFA00 0000 */
	AT   = 000
	PS   = 01
	PARE = 0
	WP   = 0
	MS   = 0 				/* GPCM */
	V    = 1				/* Valid */

	=> 0xFA00 0401

	AM            = 1111 1111 1111 1000 0	/* 8MByte */
	ATM           = 000
	CSNT/SAM      = 1
	ACS/G5LA,G5LS = 00
	BIH           = 1			/* Burst inhibited */
	SCY           = 0111		/* cycle length = 7 */
	SETA          = 0
	TRLX          = 0

	=> 0xFFF8 0970

/*### BR5 & OR5 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */

	BR5 & OR5 = 0x0000 0000		/* Not used */

/*### BR6 & OR6 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */

	BR6 & OR6 = 0x0000 0000		/* Not used */

/*### BR7 & OR7 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */

	BR7 & OR7 = 0x0000 0000		/* Not used */

/*### MAR */
/*### Memory Address Register */
/*### Chap. 16.4.7 */
/*### Offset : 0x0000 0164 */

	MA = External memory address

/*### MCR */
/*### Memory Command Register */
/*### Chap. 16.4.5 */
/*### Offset : 0x0000 0168 */

	OP   = xx			/* Command op code */
	UM   = 1			/* Select UPMA */
	MB   = 001			/* Select CS1 */
	MCLF = xxxx			/* Loop times */
	MAD  = xx xxxx		/* Memory array index */

/*### MAMR */
/*### Machine A Mode Register */
/*### Chap. 16.4.4 */
/*### Offset : 0x0000 0170 */

	PTA = 0101 1000
	PTAE = 1			/* Periodic timer A enabled */
	AMA = 010
	DSA = 00
	G0CLA = 000
	GPLA4DIS = 1
	RLFA = 0100
	WLFA = 0011
	TLFA = 0000

	=> 0x58A0 1430

/*### MBMR */
/*### Machine B Mode Register */
/*### Chap. 16.4.4 */
/*### Offset : 0x0000 0174 */

	PTA = 0100 1110
	PTAE = 0			/* Periodic timer B disabled */
	AMA = 000
	DSA = 00
	G0CLA = 000
	GPLA4DIS = 1
	RLFA = 0000
	WLFA = 0000
	TLFA = 0000

	=> 0x4E00 1000

/*### MSTAT */
/*### Memory Status Register */
/*### Chap. 16.4.3 */
/*### Offset : 0x0000 0178 */

	PER0~PER7 = Parity error
	WPER      = Write protection error

	=> 0x0000

/*### MPTPR */
/*### Memory Periodic Timer Prescaler Register */
/*### Chap. 16.4.8 */
/*### Offset : 0x0000 017A */

	PTP = 0000 1000		/* Divide by 8 */

	=> 0x0800

/*### MDR */
/*### Memory Data Register */
/*### Chap. 16.4.6 */
/*### Offset : 0x0000 017C */

	MD = Memory data contains the RAM array word


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	TIMERS */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
---------------------------------------------------------------------

/*### TBREFx */
/*### Timebase Reference Registers */
/*### Chap. 11.9.2 */
/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */
/*### (Locked) */

	TBREFF0 = 0xFFFF FFFF
	TBREFF1 = 0xFFFF FFFF

---------------------------------------------------------------------

/*### TBSCR */
/*### Timebase Status and Control Registers */
/*### Chap. 11.9.3 */
/*### Offset : 0x0000 0200 */
/*### (Locked) */

	TBIRQ = 00000000
	REF0  = 0
	REF1  = 0
	REFE0 = 0			/* Reference interrupt disable */
	REFE1 = 0
	TBF   = 1
	TBE   = 1			/* Timebase enable */

	=> 0x0003

---------------------------------------------------------------------

/*### RTCSC */
/*### Real-Time Clock Status and Control Registers */
/*### Chap. 11.10.1 */
/*### Offset : 0x0000 0220 */
/*### (Locked) */

	RTCIRQ = 00000000
	SEC = 1
	ALR = 0
	38K = 0				/* PITRTCLK is driven by 32.768KHz */
	SIE = 0
	ALE = 0
	RTF = 0
	RTE = 1				/* Real-Time clock enabled */

	=> 0x0081

---------------------------------------------------------------------

/*### RTC */
/*### Real-Time Clock Registers */
/*### Chap. 11.10.2 */
/*### Offset : 0x0000 0224 */
/*### (Locked) */

	RTC = Real time clock measured in second

---------------------------------------------------------------------

/*### RTCAL */
/*### Real-Time Clock Alarm Registers */
/*### Chap. 11.10.3 */
/*### Offset : 0x0000 022C */
/*### (Locked) */

	ALARM = 0xFFFF FFFF

---------------------------------------------------------------------

/*### RTSEC */
/*### Real-Time Clock Alarm Second Registers */
/*### Chap. 11.10.4 */
/*### Offset : 0x0000 0228 */
/*### (Locked) */

	COUNTER = Counter bits(fraction of a second)

---------------------------------------------------------------------

/*### PISCR */
/*### Periodic Interrupt Status and Control Register */
/*### Chap. 11.11.1 */
/*### Offset : 0x0000 0240 */
/*### (Locked) */

	PIRQ = 0
	PS   = 0		/* Write 1 to clear */
	PIE  = 0
	PITF = 1
	PTE  = 0		/* PIT disabled */

---------------------------------------------------------------------

/*### PITC */
/*### PIT Count Register */
/*### Chap. 11.11.2 */
/*### Offset : 0x0000 0244 */
/*### (Locked) */

	PITC = PIT count

---------------------------------------------------------------------

/*### PITR */
/*### PIT Register */
/*### Chap. 11.11.3 */
/*### Offset : 0x0000 0248 */
/*### (Locked) */

	PIT = PIT count		/* Read only */


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	CLOCKS */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
---------------------------------------------------------------------


---------------------------------------------------------------------

/*### SCCR */
/*### System Clock and Reset Control Register */
/*### Chap. 15.6.1 */
/*### Offset : 0x0000 0280 */
/*### (Locked) */

	COM    = 11		/* Clock output disabled */
	TBS    = 1		/* Timebase frequency source is GCLK2 divided by 16 */
	RTDIV  = 0		/* The clock is divided by 4 */
	RTSEL  = 0		/* OSCM(Crystal oscillator) is selected */
	CRQEN  = 0
	PRQEN  = 0
	EBDF   = 00		/* CLKOUT is GCLK2 divided by 1 */
	DFSYNC = 00		/* Divided by 1 (normal operation) */
	DFBRG  = 00		/* Divided by 1 (normal operation) */
	DFNL   = 000
	DFNH   = 000

	=> 0x6200 0000

---------------------------------------------------------------------

/*### PLPRCR */
/*### PLL, Low-Power, and Reset Control Register */
/*### Chap. 15.6.2 */
/*### Offset : 0x0000 0284 */
/*### (Locked) */

	MF    = 0x005	/* 48MHz (?) (  = 8MHz * (MF+1) ) */
	SPLSS = 0
	TEXPS = 0
	TMIST = 0
	CSRC  = 0		/* The general system clock is generated by the DFNH field */
	LPM   = 00		/* Normal high/normal low mode */
	CSR   = 0
	LOLRE = 0
	FIOPD = 0

	=> 0x0050 0000

---------------------------------------------------------------------

/*### RSR */
/*### Reset Status Register */
/*### Chap. 12.2 */
/*### Offset : 0x0000 0288 */
/*### (Locked) */

	EHRS  = External hard reset
	ESRS  = External soft reset
	LLRS  = Loss-of-lock reset
	SWRS  = Software watchdog reset
	CSRS  = Check stop reset
	DBHRS = Debug port hard reset
	DBSRS = Debug port soft reset
	JTRS  = JTAG reset


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	DMA */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
---------------------------------------------------------------------

/*### SDSR */
/*### SDMA Status Register */
/*### Chap. 20.2.2 */
/*### Offset : 0x0000 0908 */

	SBER = 0	/* SDMA channel bus error */
	DSP2 = 0	/* DSP chain2 (Tx) interrupt */
	DSP1 = 0	/* DSP chain1 (Rx) interrupt */

	=> 0x00

/*### SDMR */
/*### SDMA Mask Register */
/*### Chap. 20.2.3 */
/*### Offset : 0x0000 090C */

	SBER = 0
	DSP2 = 0
	DSP1 = 0	/* All interrupts are masked */

	=> 0x00

/*### SDAR */
/*### SDMA Address Register */
/*### Chap. 20.2.4 */
/*### Offset : 0x0000 0904 */

	AR = 0xxxxx xxxx	/* current system address */

	=> 0xFA20 23AC

/*### IDSRx */
/*### IDMA Status Register */
/*### Chap. 20.3.3.2 */
/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */

	AD   = 0
	DONE = 0
	OB   = 0

	=> 0x00

/*### IDMRx */
/*### IDMA Mask Register */
/*### Chap. 20.3.3.3 */
/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */

	AD   = 0
	DONE = 0
	OB   = 0